ZL2105ALNF Intersil, ZL2105ALNF Datasheet - Page 25

• Manufacturer Part Number: ZL2105ALNF
• Description: IC DGTL DC-DC CTRLR 3A 36QFN
• Manufacturer: Intersil
• Type: Step-Down (Buck), PWM - Voltage Moder

Specifications of ZL2105ALNF

• Internal Switch(s): Yes
• Synchronous Rectifier: Yes
• Number Of Outputs: 1
• Voltage - Output: 0.6 V ~ 5.5 V
• Current - Output: 3A
• Frequency - Switching: 200kHz ~ 2MHz
• Voltage - Input: 4.5 V ~ 14 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2 Power Good (PG) and Output Overvoltage
The ZL2105 provides a Power Good (PG) signal that
indicates the output voltage is within a specified
tolerance of its target level and no fault condition
exists. By default, the PG pin will assert if the output is
within +15%/-10% of the target voltage. These limits
may be changed via the I
A PG delay period is defined as the time from when all
conditions for asserting PG are met and when the PG
pin is actually asserted. This feature is commonly used
instead of an external reset controller to signal the
power supply is at its target voltage prior to enabling
any powered circuitry. By default, the ZL2105 PG
delay is set equal to the soft-start ramp time setting.
Thus if the soft-start ramp time is set to 10ms, the PG
pin will assert 10ms after the output is within its
specified tolerance band. The PG delay period can be
set independent of the soft-start ramp time via the
I
6.3 Output Overvoltage Protection
The ZL2105 offers an internal output overvoltage
protection circuit that can be used to protect sensitive
load circuitry from being subjected to a voltage higher
than its prescribed limits. A hardware comparator is
used to compare the actual output voltage (seen at the
VSEN pin) to a threshold set to 15% higher than the
target output voltage (the default setting). If the VSEN
voltage exceeds this threshold, the PG pin will de-
assert and the device can then respond in a number of
ways as follows:
1. Initiate an immediate shutdown until the fault has
2. Turn off the high-side MOSFET and turn on the
2
C/SMBus interface.
Protection
been cleared. The user can select a specific number
of retry attempts.
low-side MOSFET. The low-side MOSFET
remains on until the device attempts a restart.
25
2
C/SMBus interface.
ZL2105
The default response from an overvoltage fault is to
immediately shut down. The device will continuously
check for the presence of the fault condition, and when
the fault condition no longer exists the device will be
re-enabled.
For continuous overvoltage protection when operating
from an external clock, the only allowed response is an
immediate shutdown.
Please refer to Application Note AN2013 for details on
how to select specific overvoltage fault response
options via I
6.4 Output Pre-Bias Protection
An output pre-bias condition exists when an externally
applied voltage is present on a power supply’s output
before the power supply’s control IC is enabled.
Certain applications require that the converter not be
allowed to sink current during start up if a pre-bias
condition exists at the output. The ZL2105 provides
pre-bias protection by sampling the output voltage
prior to initiating an output ramp.
If a pre-bias voltage lower than the target voltage exists
after the pre-configured delay period has expired, the
target voltage is set to match the existing pre-bias
voltage and both drivers are enabled. The output
voltage is then ramped to the final regulation value at
the ramp rate set by the SS pin. The actual time the
output will take to ramp from the pre-bias voltage to
the target voltage will vary depending on the pre-bias
voltage but the total time elapsed from when the delay
period expires and when the output reaches its target
value will match the pre-configured ramp time. See
Figure 17.
2
C/SMBus.
March 30, 2011
FN6851.2