STLM75M2E STMicroelectronics, STLM75M2E Datasheet - Page 22

• Manufacturer Part Number: STLM75M2E
• Description: IC TEMP SENSOR DIGITAL SO-8
• Manufacturer: STMicroelectronics

Specifications of STLM75M2E

• Featured Product: STM32 Cortex-M3 Companion Products
• Function: Temp Sensor, Watchdog
• Topology: ADC (Sigma Delta), Comparator, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -55°C ~ 125°C
• Output Type: I²C™/SMBus™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Full Temp Accuracy: +/- 3 C
• Digital Output - Bus Interface: Serial (2-Wire, I2C)
• Digital Output - Number Of Bits: 9 bit
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Ic Output Type: Digital
• Sensing Accuracy Range: ± 0.5°C
• Temperature Sensing Range: -55°C To +125°C
• Supply Current: 125µA
• Supply Voltage Range: 2.7V To 5.5V
• Sensor Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• For Use With: 497-10508 - BOARD EVAL FOR MEMS SENSORS497-10048 - BOARD EVAL ACCELEROMETER497-6238 - BOARD STLM75/STDS75/ST72F651
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Functional description
3.4.5
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Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse (see
generate an acknowledge after the reception of each byte that has been clocked out of the
slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 7.
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
Acknowledgement sequence
START
Figure
MSB
1
Doc ID 13296 Rev 12
7). A slave receiver which is addressed is obliged to
2
LSB
8
ACKNOWLEDGEMENT
CLOCK PULSE FOR
9
STLM75
AI00601