LE24LB642CSTL-TFM-H SANYO, LE24LB642CSTL-TFM-H Datasheet - Page 8

• Manufacturer Part Number: LE24LB642CSTL-TFM-H
• Description: IC EEPROM 64KBIT 400KHZ WLP6
• Manufacturer: SANYO

Specifications of LE24LB642CSTL-TFM-H

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 6-XFBGA, 6-WLBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 869-1238-2; LE24LB642CS-TFM-H

SDA
7-2. Random read
7-3. Sequential read
Random read is a mode in which a selected memory address is specified and its data is read. The address is specified
by a dummy write input.
First, when the EEPROM receives the 7-bit device address and write command code "0" following the start condition,
it generates an acknowledge signal. It then receives 3-bit don’t-care bits and a 13-bit word address and generates an
acknowledge signal. These operations are used to load the word address to the address counter in the EEPROM.
Next, the start condition is input again, and the current read is performed. This generates the word address data that
was input using the dummy write input. After the data is generated, if the stop condition is input without the input of
an acknowledge signal, reading is completed, and standby mode is established.
In this mode, the data is read continuously, and sequential read operations can be performed with both current address
read and random read. If, after the 8-bit data has been output, acknowledge “0” is input and reading is continued
without issuing the stop condition, the address is incremented, and the data of the next address is output.
If acknowledge “0” continues to be input after the data has been output in this way, the data is successively output
while the address is incremented. When the last address is reached, it is rolled over to address 0, and the data
continues to be read. As with current address read and random read, the operation is completed by inputting the stop
condition without sending an acknowledge signal.
SDA
1
Device Address
0 1 0
1
Device Address
S2
0 1 0
S1
S0
S2
R
R/W
S1
ACK
S0
D7 D6 - D1 D0
W
Data(n)
R/W
ACK
*
*
LE24LB642CS
*
Dummy Write
12
ACK
A
D7 D6 - D1 D0
11
A
Data(n+1)
10
A
ACK
A9 A8
1
Device Address
Word Address(n)
0 1 0
ACK
A7 A6 A5 A4 A3 A2 A1 A0
ACK
D7 D6 - D1 D0
Data(n+2)
S2
S1
Current Read
S0
R
R/W
ACK
ACK
D7 D6 - D1 D0
D7 D6 - D1 D0
Data(n+x)
ACK
Data(n)
No.A1464-8/11
*: don’t care
NO ACK
NO ACK