le24lb642cs Sanyo Semiconductor Corporation, le24lb642cs Datasheet
le24lb642cs
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le24lb642cs Summary of contents
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... LE24LB642CS Overview The LE24LB642CS is a 2-wire serial interface EEPROM. It realizes high speed and a high level reliability by incorporating SANYO’s high performance CMOS EEPROM technology. This device is compatible with I protocol, therefore it is best suited for application that requires small-scale re-writable nonvolatile parameter memory. ...
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... Supply voltage DC input voltage Over-shoot voltage Storage temperature Tstg Note electrical stress exceeding the maximum rating is applied, the device may be damaged. Operating Conditions Parameter Symbol Operating supply voltage Operating temperature LE24LB642CS Pin Descriptions PIN.1 PIN.2 6 PIN.3 PIN.4 PIN.5 1 PIN.6 Write controller ...
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... Data in setup time Data in hold time Stop condition setup time SCL SDA rise time SCL SDA fall time Bus release time Noise suppression time Write cycle time LE24LB642CS Symbol Conditions f=400kHz f=400kHz GND V IN =GND OUT =GND ...
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... WP (write protect) pin When the WP pin is high, write protection is enabled, and writing into the 64k bit memory areas is prohibited. When the pin is low, writing is possible to all memory areas. Read operations can be performed regardless of the WP pin status. LE24LB642CS t HIGH t LOW SU.DAT t HD ...
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... SDA line to low, and sends the acknowledge signal indicating that the data has been received. The acknowledge signal is not sent during an EEPROM internal write operation. SCL (EEPROM input) SDA (Master output) SDA (EEPROM output) Start condition LE24LB642CS t HD.DAT SU.STO Stop condition 9 Acknowledge bit output ...
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... Finally, the EEPROM internal write operation corresponding to the page size for which the write data is received starts from the designated memory address when the stop condition is received. LE24LB642CS Device Code 0 ...
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... If the write data more bytes the designated word address. If the last address (A4-A0=11111b) on the page has been designated by byte write as the word address, the first address (A4-A0=00000b) on the page serves as the internal address after writing. SDA LE24LB642CS Word Address( ...
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... When the last address is reached rolled over to address 0, and the data continues to be read. As with current address read and random read, the operation is completed by inputting the stop condition without sending an acknowledge signal. Device Address SDA R/W LE24LB642CS Word Address( ...
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... set to strike a good balance between the operating frequency requirements and power consumption assumed that the SDA load capacitance is 50pF and the SDA output data strobe time is 500ns will be about 500ns/50pF = 10kΩ. LE24LB642CS Dummy clock cycle × ...
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... not possible to satisfy the instruction 1 in Note above, and SDA is set to low during power rise After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins set to high SCL SDA t DH LE24LB642CS V DD =1.7 to 3.6V Symbol min t SU.WP 600 t HD ...
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... SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2009. Specifications and information herein are subject to change without notice. LE24LB642CS PS No.A1464-11/11 ...