MCZ33905BS3EK Freescale Semiconductor, MCZ33905BS3EK Datasheet - Page 69

• Manufacturer Part Number: MCZ33905BS3EK
• Description: IC SBC CAN HS 3.3V 32SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MCZ33905BS3EK

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 16. Initialization Watchdog Registers, INIT watchdog (note: register can be written only in INIT Mode)
no watchdog
no watchdog
no watchdog
no watchdog
watchdog +
watchdog +
watchdog +
watchdog +
[b_15 b_14] 0_0110 [P/N]
b6, b5
b3, b2
MOSI First Byte [15-8]
+ 00
+ 01
+ 10
+ 11
Bit
Condition for default
b7
00
01
10
11
b4
00
01
10
11
b1
0
1
0
1
0
1
01 00 _ 110 P
Default state
MCU_OC, OC-TIM - In LP V
In LP V
In LP V
threshold for a time > I_mcu_OC is Wake-Up event. I_mcu_OC time is selected in Timer register (selection range from 3.0 to 32 ms)
DD
DD
ON Mode, V
In LP V
In LP V
ON Mode, V
INT source read must occur before the remaining of the current watchdog period plus 2 complete watchdog periods.
In LP V
Watchdog operation is WINDOW, watchdog refresh must occur in the open window (second half of period)
DD
DD
WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command
WD2INT
bit 7
DD
ON Mode, V
ON Mode, V
WD Safe - Select the activation of the SAFE pin low, at first or second consecutive RESET pulse
0
DD
DD
current > V
In LP V
DD
current > V
ON Mode, V
Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.
Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command.
Watchdog operation is TIMEOUT, watchdog refresh can occur anytime in the period
ON, select watchdog refresh and V
Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits.
Function disable. No constraint between INT occurrence and INT source read.
Simple Watchdog selection: watchdog refresh done by a 8 bits or 16 bits SPI
WD N/Win - Select the Watchdog (watchdog) Window or Timeout operation
DD
MCU_OC
DD
DD
DD_OC_LP
bit 6
ON Mode, V
WD_spi[1] WD_spi[0] - Select the Watchdog (watchdog) Operation
current > V
current > V
SAFE pin is set low at the second consecutive time RESET pulse
1
DD_OC_LP
SAFE pin is set low at the time of the RESET pin low activation
DD
current > V
In LP V
In LP V
threshold for a time > I_mcu_OC is a Wake-Up event. I_mcu_OC time is selected in Timer register
DD_OC_LP
DD_OC_LP
In LP Mode, when watchdog is not selected
threshold for a time < I_mcu_OC is a watchdog refresh condition. V
DD
OC-TIM
In LP Mode when watchdog is selected
bit 5
electrical parameters (approx 1.5 mA)
DD
DD
over-current for a time > 100 μs (typically) is a Wake-Up event.
(selection range from 3.0 to 32 ms)
0
DD_OC_LP
ON Mode, V
ON Mode, V
threshold has no effect. watchdog refresh must occur by SPI command.
threshold has no effect. watchdog refresh must occur by SPI command.
Description
WD Safe
MOSI Second Byte, bits 7-0
threshold for a time > 100 μs (typically) is a Wake-Up event
DD
bit 4
DD
DD
current monitoring functionality. V
over-current has no effect
over-current has no effect
POR
DETAIL OF CONTROL BITS AND REGISTER MAPPING
WD_spi[1]
bit 3
0
WD_spi[0]
bit 2
0
SERIAL PERIPHERAL INTERFACE
DD_OC_LP
threshold is defined in device
WD N/Win
bit 1
DD
1
current > V
DD_OC_LP
Crank
bit 0
33903/4/5
0
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