ML610Q412P-NNNTB03A7 Rohm Semiconductor, ML610Q412P-NNNTB03A7 Datasheet - Page 321

• Manufacturer Part Number: ML610Q412P-NNNTB03A7
• Description: MCU 8BIT 16K FLASH 120-TQFP
• Manufacturer: Rohm Semiconductor

Specifications of ML610Q412P-NNNTB03A7

• Core Processor: nX-U8/100
• Core Size: 8-Bit
• Speed: 625kHz
• Connectivity: I²C, SSP, UART/USART
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 2x12b, 2x24b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

25.3 Description of Operation
25.3.1
According to the setting of SA-ADC mode register 0 (SADMOD0), A/D conversion is performed as shown below and
A/D conversion results are stored in the SA-ADC result register.
The values of the result register for the sections with a slash mark remain unchanged.
Do not start A/D conversion when bits 1 (SACH1) and 0 (SACH0) of SA-ADC mode register 0 (SADMOD0) are 0
and 0. If A/D conversion is started, the A/D conversion circuit is set to ON. However, as A/D conversion is not
performed, the SA-ADC result register is not updated, an A/D conversion termination interrupt is not generated, A/D
conversion does not terminate automatically, and bit 0 (SARUN) of the SA-ADC control register (SADCON1) remains
“1”.
If the A/D conversion resolution is enough as required when analog input signals are converted by direct A/D
conversion and the A/D conversion result range for the analog input change range satisfies the requirement, select
direct input. For the direct input settings, set bits 1 and 0 of the amplifier controller register 0 (AMPCON0) to 0.
Since the amplifier is not used, the amplifier settling time is not required.
In direct A/D conversion, the A/D conversion result increases when the input voltage increases.
Direct input
SA-ADC
mode register 0
SACH0/1
SACH0
SACH1
SACH0
SACH1
SACH0
SACH1
Settings of A/D Conversion Channels
AV
AV
AIN
V
REF
DD
SS
x
0/1
0
1
1
0
1
1
Figure 25-2 A/D conversion pins and conversion range
SA-ADC result register
SADR0
SADR1
SADR0
SADR1
SADR0
SADR1
Chapter 25 Successive Approximation Type A/D Converter
V
ADIN
25 – 9
ML610Q411/ML610Q412/ML610Q415 User’s Manual
AIN1 input
AIN0 input
AIN0 input
AIN1 input
approximation
successive
converter
type A/D
12-bit
Analog input
variation range
A/D conversion input voltage
V
ADIN
V
AV
REF
SS