PCF8564ACX9/B/1,02 NXP Semiconductors, PCF8564ACX9/B/1,02 Datasheet - Page 7

• Manufacturer Part Number: PCF8564ACX9/B/1,02
• Description: IC RTC/CALENDAR
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF8564ACX9/B/1,02

• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: Die
• Function: Serial Clock, Alarm, Calendar, Timer, Timer Interrupt
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C
• Supply Current: 1700 nA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed
• Other names: 568-6424-2; PCF8564ACX9/B/1,02

NXP Semiconductors
Table 5.
[1]
[2]
Table 6.
[1]
[2]
PCF8564A
Product data sheet
Bit
7
6
5
4
3
2 to 0
Bit
7 to 5
4
3
2
1
0
Default value.
Bits labeled as N should always be written with logic 0.
Bits labeled as N should always be written with logic 0.
Default value.
Symbol
TEST1
N
STOP
N
TESTC
N
Symbol
N
TI_TP
AF
TF
AIE
TIE
Control_1 - control and status register 1 (address 00h) bit description
Control_2 - control and status register 2 (address 01h) bit description
8.3.1 Register Control_1
8.3.2 Register Control_2
8.3 Control registers
Value
0
1
0
0
1
0
0
1
000
Value
000
0
1
0
1
0
1
0
1
0
1
[1]
[2]
[1]
[2]
[1]
[2]
[2]
[2]
[2]
[2]
[2]
[1]
Power-On Reset (POR) override facility is disabled;
Description
normal mode;
EXT_CLK test mode (see
default value
RTC source clock runs
default value
Power-On Reset (POR) override is enabled
default value
Description
default value
INT is active when TF is active (subject to the status of TIE)
INT pulses active according to
alarm flag inactive
alarm flag active
timer flag inactive
timer flag active
alarm interrupt disabled
alarm interrupt enabled
timer interrupt disabled
timer interrupt enabled
•
•
•
•
•
must be set to logic 0 during normal operations
RTC divider chain flip-flops are asynchronously set to logic 0
the RTC clock is stopped (CLKOUT at 32.768 kHz is still available)
set to logic 0 for normal operation (see
Remark: note that if AF and AIE are active then INT will be
permanently active
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 30 September 2010
Section
Table 7
8.9)
(subject to the status of TIE);
Section
8.11.1)
Real time clock and calendar
PCF8564A
© NXP B.V. 2010. All rights reserved.
Reference
Section 8.9
Section 8.10
Section 8.11.1
Reference
Section 8.3.2.1
and
Section 8.8
Section 8.3.2.1
Section 8.3.2.1
Section 8.3.2.1
Section 8.3.2.1
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