LFE3-150EA-7FN1156CTW Lattice, LFE3-150EA-7FN1156CTW Datasheet - Page 72

• Manufacturer Part Number: LFE3-150EA-7FN1156CTW
• Description: FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -7 Speed
• Manufacturer: Lattice

Specifications of LFE3-150EA-7FN1156CTW

• Number Of Programmable I/os: 133 to 586
• Data Ram Size: 6.85 Mbits
• Delay Time: 37 ns
• Supply Voltage (max): 1.26 V
• Supply Current: 18 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-1156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeECP3 External Switching Characteristics (Continued)
Lattice Semiconductor
Generic DDRX2 Output with Clock and Data (> 10 Bits Wide) Aligned at Pin (GDDRX2_TX.ECLK.Aligned)
Left and Right Sides
t
t
f
Generic DDRX2 Outputs with Clock and Data Edges Aligned, Without PLL 90-degree shifted clock output
(GDDRX2_TX.Aligned)
t
t
f
Generic DDRX2 Output with Clock and Data (> 10 Bits Wide) Centered at Pin Using DQSDLL (GDDRX2_TX.DQS-
DLL.Centered)
Left and Right Sides
t
t
f
Generic DDRX2 Output with Clock and Data (> 10 Bits Wide) Centered at Pin Using PLL (GDDRX2_TX.PLL.Centered)
Left and Right Sides
t
t
f
Generic DDRX2 Outputs with Clock Edge in the Center of Data Window, with PLL 90-degree Shifted Clock Output
(GDDRX2_TX.PLL.Centered)
t
t
f
Memory Interface
DDR/DDR2 SDRAM I/O Pin Parameters (Input Data are Strobe Edge Aligned, Output Strobe Edge is Data Centered)
t
t
t
t
f
f
t
t
t
t
f
DIBGDDR
DIAGDDR
MAX_GDDR
DIBGDDR
DIAGDDR
MAX_GDDR
DVBGDDR
DVAGDDR
MAX_GDDR
DVBGDDR
DVAGDDR
MAX_GDDR
DVBGDDR
DVAGDDR
MAX_GDDR
DVADQ
DVEDQ
DQVBS
DQVAS
MAX_DDR
MAX_DDR2
DVADQ
DVEDQ
DQVBS
DQVAS
MAX_DDR
Parameter
Parameter
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Invalid Before Clock
Data Invalid After Clock
DDR/DDRX2 Clock Frequency
Data Valid Before CLK
Data Valid After CLK
DDRX2 Clock Frequency
Data Valid Before CLK
Data Valid After CLK
DDRX2 Clock Frequency
Data Valid Before CLK
Data Valid After CLK
DDR/DDRX2 Clock Frequency
Data Valid After DQS (DDR Read)
Data Hold After DQS (DDR Read)
Data Valid Before DQS
Data Valid After DQS
DDR Clock Frequency
DDR2 clock frequency
Data Valid After DQS (DDR Read)
Data Hold After DQS (DDR Read)
Data Valid Before DQS
Data Valid After DQS
DDR Clock Frequency
Over Recommended Commercial Operating Conditions
Description
Description
8
8
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
3-20
Device
Device
Min.
Min.
0.64
0.25
0.25
0.64
0.25
0.25
300
300
133
95
95
—
—
—
—
—
—
—
—
—
—
—
DC and Switching Characteristics
-8
-8
LatticeECP3 Family Data Sheet
0.225
0.225
Max.
Max.
200
200
500
500
200
266
200
—
—
—
—
—
—
—
—
—
—
—
—
Min.
Min.
0.64
0.25
0.25
0.64
0.25
0.25
370
370
133
95
95
—
—
—
—
—
—
—
—
—
—
—
-7
-7
0.225
0.225
Max.
Max.
225
225
420
420
200
200
200
1, 2
—
—
—
—
—
—
—
—
—
—
—
—
Min.
Min.
0.64
0.25
0.25
0.64
0.25
0.25
417
417
133
—
95
—
95
—
—
—
—
—
—
—
—
—
-6
-6
5
0.225
0.225
Max.
Max.
250
250
375
375
166
166
133
—
—
—
—
—
—
—
—
—
—
—
—
Units
Units
MHz
MHz
MHz
MHz
MHz
MHz
6
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ps
ps
UI
UI
UI
UI
UI
UI
UI
UI
4