LFE3-150EA-7FN1156CTW Lattice, LFE3-150EA-7FN1156CTW Datasheet - Page 48

• Manufacturer Part Number: LFE3-150EA-7FN1156CTW
• Description: FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -7 Speed
• Manufacturer: Lattice

Specifications of LFE3-150EA-7FN1156CTW

• Number Of Programmable I/os: 133 to 586
• Data Ram Size: 6.85 Mbits
• Delay Time: 37 ns
• Supply Voltage (max): 1.26 V
• Supply Current: 18 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-1156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-40. SERDES/PCS Quads (LatticeECP3-150)
Table 2-13. LatticeECP3 SERDES Standard Support
PCI Express 1.1
Gigabit Ethernet
SGMII
XAUI
Serial RapidIO Type I,
Serial RapidIO Type II,
Serial RapidIO Type III
CPRI-1,
CPRI-2,
CPRI-3,
CPRI-4
SD-SDI
(259M, 344M)
HD-SDI
(292M)
3G-SDI
(424M)
SONET-STS-3
SONET-STS-12
SONET-STS-48
1. For slower rates, the SERDES are bypassed and CML signals are directly connected to the FPGA routing.
2. The SONET protocol is supported in 8-bit SERDES mode. See TN1176
Standard
2
2
2
sysIO Bank 0
SERDES/PCS
1250, 2500
Quad D
Data Rate
(Mbps)
1228.8,
2457.6,
1483.5,
3072.0
155.52
622.08
614.4,
1250,
2500,
2967,
2500
1250
3125
3125
143
177
1485
2970
2488
270,
360,
540
1
1
,
,
SERDES/PCS
Quad B
2-45
SERDES/PCS
Quad A
Lattice ECP3 SERDES/PCS Usage Guide
sysIO Bank 1
General/Link Width
Number of
x1, x2, x4
x1, x4
SERDES/PCS
x1
x1
x4
x1
x1
x1
x1
x1
x1
x1
Quad C
LatticeECP3 Family Data Sheet
NRZI/Scrambled
NRZI/Scrambled
NRZI/Scrambled
Encoding Style
for more information.
8b10b
8b10b
8b10b
8b10b
8b10b
8b10b
Architecture
N/A
N/A
N/A