LFE3-150EA-7FN1156CTW Lattice, LFE3-150EA-7FN1156CTW Datasheet - Page 18
LFE3-150EA-7FN1156CTW
Manufacturer Part Number
LFE3-150EA-7FN1156CTW
Description
FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -7 Speed
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672CTW.pdf
(130 pages)
Specifications of LFE3-150EA-7FN1156CTW
Number Of Programmable I/os
133 to 586
Data Ram Size
6.85 Mbits
Delay Time
37 ns
Supply Voltage (max)
1.26 V
Supply Current
18 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-1156
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE3-150EA-7FN1156CTW
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
secondary clock resources per region (SC0 to SC7). The same secondary clock routing can be used for control
signals.
Table 2-6. Secondary Clock Regions
Figure 2-15. LatticeECP3-70 and LatticeECP3-95 Secondary Clock Regions
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Region R1C1
Region R2C1
Region R3C1
Region R4C1
Region R5C1
sysIO Bank 0
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Region R1C2
Region R2C2
Region R3C2
Region R4C2
Region R5C2
ECP3-150
ECP3-17
ECP3-35
ECP3-70
ECP3-95
Device
Spine Repeaters
SERDES
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Region R1C3
Region R2C3
Region R3C3
Region R4C3
Region R5C3
Number of Secondary Clock
sysIO Bank 1
2-15
Regions
Vertical Routing Channel
16
16
20
20
36
Regional Boundary
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Secondary Clock
Region R1C4
Region R2C4
Region R3C4
Region R4C4
Region R5C4
LatticeECP3 Family Data Sheet
Regional Boundary
Regional Boundary
EBR Row
EBR Row
Architecture
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