LFE3-150EA-7FN1156CTW Lattice, LFE3-150EA-7FN1156CTW Datasheet - Page 71

• Manufacturer Part Number: LFE3-150EA-7FN1156CTW
• Description: FPGA - Field Programmable Gate Array 149K LUTs 586 I/O 1.2V -7 Speed
• Manufacturer: Lattice

Specifications of LFE3-150EA-7FN1156CTW

• Number Of Programmable I/os: 133 to 586
• Data Ram Size: 6.85 Mbits
• Delay Time: 37 ns
• Supply Voltage (max): 1.26 V
• Supply Current: 18 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-1156
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeECP3 External Switching Characteristics (Continued)
Lattice Semiconductor
t
f
Generic DDRX2 Inputs with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX2_RX.DQS.Centered) using DQS
Pin for Clock Input
Left and Right Sides
t
t
f
Generic DDRX2 Inputs with Clock and Data (<10 Bits Side) Aligned at Pin (GDDRX2_RX.DQS.Aligned) Using DQS Pin
for Clock Input
Left and Right Sides
t
t
f
Generic DDRX1 Output with Clock and Data (>10 Bits Wide) Centered at Pin (GDDRX1_TX.SCLK.Centered)
Left, Right and Top Sides
t
t
f
Generic DDRX1 Outputs with clock in the center of data window, with PLL 90-degree shifted clock ouput
(GDDRX1_TX.ECLK.Centered)
t
t
fMAX_GDDR
Generic DDRX1 Output with Clock and Data (> 10 Bits Wide) Aligned at Pin (GDDRX1_TX.SCLK.Aligned)
Left, Right and Top Sides
t
t
f
Generic DDRX1 Outputs with clock and data edge aligned, without PLL
t
t
f
Generic DDRX1 Output with Clock and Data (<10 Bits Wide) Centered at Pin (GDDRX1_TX.DQS.Centered)
Left, Right and Top Sides
t
t
f
DVECLKGDDR
MAX_GDDR
SUGDDR
HGDDR
MAX_GDDR
DVACLKGDDR
DVECLKGDDR
MAX_GDDR
DVBGDDR
DVAGDDR
MAX_GDDR
DIBGDDR
DIAGDDR
DIBGDDR
DIAGDDR
MAX_GDDR
DIBGDDR
DIAGDDR
MAX_GDDR
DVBGDDR
DVAGDDR
MAX_GDDR
Parameter
Data Hold After CLK
DDR/DDRX2 Clock Frequency
Data Setup Before CLK
Data Hold After CLK
DDRX2 Clock Frequency
Data Setup Before CLK (Left and
Right Side)
Data Hold After CLK (Left and Right
Side)
DDRX2 Clock Frequency (Left and
Right Side)
Data Valid Before CLK
Data Valid After CLK
DDRX1 Clock Frequency
Data Invalid Before CLK
Data Invalid After CLK
DDRX1 Clock Frequency
Data Hold After CLK
Data Setup Before CLK
DDRX1 Clock Frequency
Data Invalid Before CLK
Data Invalid After CLK
DDRX1 Clock Frequency
Data Valid Before CLK
Data Valid After CLK
DDRX1 Clock Frequency
Over Recommended Commercial Operating Conditions
Description
8
ECP3-70E/95E 0.765
ECP3-70E/95E
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
ECP3-150EA
ECP3-150EA
ECP3-150EA
ECP3-70E/95E
ECP3-70E/95E
ECP3-70E/95E
ECP3-150EA
ECP3-150EA
ECP3-150EA
3-19
Device
Min.
670
670
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC and Switching Characteristics
-8
LatticeECP3 Family Data Sheet
Max.
500
250
330
330
250
—
—
—
—
—
—
—
—
0.765
Min.
670
670
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-7
Max.
420
250
330
330
250
1, 2
—
—
—
—
—
—
—
—
0.765
Min.
670
670
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
Max.
375
250
330
330
250
—
—
—
—
—
—
—
—
Units
MHz
MHz
MHz
ns
ns
ns
ps
ps
ps
ps
UI