A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 21

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HiRel SX-A Timing Model
Note: *Values shown for are HiRel A54SX72A–1, worst-case military conditions for V
Figure 1-15 • HiRel SX-A Timing Model
Hardwired Clock
External Setup
Clock-to-Out (Pin-to-Pin)
= t
= 1.0 + 0.5 + 1.0 - 2.2 = 0.3ns
= t
= 2.2 + 1.0 + 0.5 + 4.5 = 8.2 ns
INYH
HCKL
Hardwired
Routed
+ t
+ t
Clock
Clock
RD1
RCO
+ t
+ t
SUD
RD1
– t
+ t
t
t
Input Delays
I/O Module
HCKL
INYH
INYH
I/O Module
DHL
= 1.0 ns
= 1.0 ns
t
(100% Load)
t
RCKH
HCKL
= 2.2 ns
= 3.9 ns
t
t
IRD1
IRD2
t
t
t
t
SUD
HD
SUD
HD
= 0.5 ns
= 0.7 ns
= 0.0 ns
= 0.0 ns
= 1.0 ns
= 1.0 ns
EQ 1-8
EQ 1-9
Internal Delays
Combinatorial
t
t
t
v2.0
RCO
RCO
PD
Register
Register
D
D
= 1.2 ns
Cell
Cell
Cell
Routed Clock
External Setup
Clock-to-Out (Pin-to-Pin)
= 1.0 ns
= 1.0 ns
= t
= 1.0 + 0.5 + 1.0 - 3.9 = -1.4 ns
= t
= 3.9 + 1.0 + 0.5 + 4.5 = 9.9 ns
Q
Q
INYH
RCKH
+ t
+ t
t
t
t
t
t
CCI
Predicted
RD1
RD4
RD8
RD1
RD1
Routing
RD1
RCO
Delays
= 3.0 V.
= 0.5 ns
= 1.2 ns
= 2.0 ns
= 0.5 ns
= 0.5 ns
+ t
+ t
SUD
RD1
– t
+ t
RCKH
DHL
Output Delays
t
t
t
t
t
ENZL
ENZL
I/O Module
I/O Module
I/O Module
DHL
DHL
DHL
HiRel SX-A Family FPGAs
= 4.5 ns
= 4.5 ns
= 2.9 ns
= 4.5 ns
= 2.9 ns
EQ 1-10
EQ 1-11
1-17