A54SX32A-PQ208 Actel, A54SX32A-PQ208 Datasheet - Page 11

• Manufacturer Part Number: A54SX32A-PQ208
• Description: FPGA - Field Programmable Gate Array 32K System Gates
• Manufacturer: Actel

Specifications of A54SX32A-PQ208

• Processor Series: A54SX32
• Core: IP Core
• Number Of Macrocells: 1800
• Maximum Operating Frequency: 238 MHz
• Number Of Programmable I/os: 174
• Delay Time: 1.2 ns
• Supply Voltage (max): 5.25 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.25 V
• Number Of Gates: 48 K
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Hot-Swapping
HiRel SX-A I/Os can be configured to be hot-swappable in
compliance
However, a 3.3 V PCI device is not hot-swappable. During
power-up/down, all I/Os are tristated. V
not have to be stable during power-up/down. After the
HiRel SX-A device is plugged into an electrically active
system, it will not degrade the reliability of or cause
damage to the host system. The device’s output pins are
driven to a high impedance state until normal chip
Table 1-4 •
Power Requirements
The HiRel SX-A family supports 2.5 V/3.3 V/5 V mixed-
voltage operation and is designed to tolerate 5 V inputs
for all standards except 3.3 V PCI. In PCI mode, I/Os
support 3.3 V or 5 V, and input tolerance depends on
V
page 1-12
extremely low due to the very short distances signals are
required to travel to complete a circuit. Power
requirements are further reduced due to the small
number of antifuses in the path and the low-resistance
properties of the antifuses. The antifuse architecture
does not require active circuitry to hold a charge (as do
SRAM
architecture on the market.
Boundary Scan Testing (BST)
All HiRel SX-A devices are IEEE 1149.1 compliant. HiRel
SX-A devices offer superior diagnostic and testing
capabilities by providing BST and probing capabilities.
The BST function is controlled through the special JTAG
pins (TMS, TDI, TCK, TDO, and TRST). The functionality of
the JTAG pins is defined by one of two available modes:
Dedicated and Flexible
employed as a user I/O in either mode.
Table 1-5 •
Ramp Rate
Units
HiRel A54SX32A
HiRel A54SX72A
Program Fuse Blown
(Dedicated Test Mode)
TCK, TDI, TDO are dedicated
BST pins.
No need for pull-up resistor for
TMS.
CCI
. Refer to
or
for more information. Power consumption is
EPROM),
Power-Up Time at which I/Os Become Active
Boundary Scan Pin Functionality
with
Table 1-8 on page 1-11
the
0.25 V/µs
making
µs
10
10
Compact
(Table
Program Fuse Not Blown
(Flexible Mode)
TCK, TDI, TDO are flexible and
may be used as I/Os.
Use a pull-up resistor of 10 kΩ
on TMS.
0.025 V/µs
1-5). TMS cannot be
it
100
100
µs
the
PCI
and
CCA
Table 1-10 on
lowest-power
Specification.
and V
5 V/ms
0.46
0.41
ms
CCI
do
v2.0
2.5 V/ms
0.74
0.67
ms
operating conditions are reached.
the V
the user’s design for a HiRel SX-A device at room
temperature for various ramp-up rates. The data
reported assumes a linear ramp-up profile to 2.5 V. Refer
to the Actel application note
Devices in Hot-Swap and Cold-Sparing Applications
more information on hot-swapping.
Configuring Diagnostic Pins
The JTAG and probe pins (TDI, TCK, TMS, TDO, PRA, and
PRB) are placed in the desired mode by selecting the
appropriate check boxes in the Variation dialog
window. This dialog window is accessible through the
Design Setup Wizard under the Tools menu in the Actel
Designer software.
If JTAG I/Os (except TMS) are not programmed as
dedicated JTAG I/Os, they can be used as regular I/Os.
TRST Pin
When the Reserve JTAG Test Reset box is checked, the
TRST pin will become a Boundary Scan Reset pin. In this
mode,
asynchronous, active low input to initialize or reset the
BST circuit. An internal pull-up resistor will be enabled
automatically on the TRST pin.
The TRST pin will function as a user I/O when the
Reserve JTAG Test Reset check box is cleared. The
internal pull-up resistor will be disabled in this mode.
Dedicated Test Mode
When the Reserve JTAG box is checked in the Designer
software, the HiRel SX-A device is placed in Dedicated
Test mode, which configures the TDI, TCK, and TDO pins
for BST or in-circuit verification with Silicon Explorer II.
An internal pull-up resistor is automatically enabled on
both the TMS and TDI pins. In Dedicated Test mode, TCK,
TDI, and TDO are dedicated test pins and become
unavailable for pin assignment in the Pin Editor. The TMS
pin will function as specified in the IEEE 1149.1 (JTAG)
specification.
CCA
0.5 V/ms
the
voltage at which the I/Os behave according to
ms
2.8
2.6
TRST
0.25 V/ms
pin
ms
5.2
5.0
functions
Actel SX-A and RT54SX-S
HiRel SX-A Family FPGAs
0.1 V/ms
Table 1-4
12.1
12.1
ms
as
a
0.025 V/ms
summarizes
dedicated,
47.2
47.2
ms
1-7
for