A42MX09-PQG100 Actel, A42MX09-PQG100 Datasheet - Page 81

• Manufacturer Part Number: A42MX09-PQG100
• Description: FPGA - Field Programmable Gate Array 14K System Gates
• Manufacturer: Actel

Specifications of A42MX09-PQG100

• Processor Series: A42MX09
• Core: IP Core
• Number Of Macrocells: 336
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 104
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 14 K
• Package / Case: PQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 39 •
Parameter Description
Input Module Predicted Routing Delays
t
t
t
t
t
Global Clock Network
t
t
t
t
t
t
t
t
f
TTL Output Module Timing
t
t
t
t
t
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
IRD1
IRD2
IRD3
IRD4
IRD8
CKH
CKL
PWH
PWL
CKSW
SUEXT
HEXT
P
MAX
DLH
DHL
ENZH
ENZL
ENHZ
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer utility.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued)
(Worst-Case Commercial Conditions, V
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Input LOW to HIGH
Input HIGH to LOW
Minimum Pulse
Width HIGH
Minimum Pulse
Width LOW
Maximum Skew
Input Latch
External Set-Up
Input Latch
External Hold
Minimum Period
(1/f
Maximum Datapath
Frequency
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
MAX
)
5
PD1
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
FO=32
FO=635
+ t
RD1
+ t
2
PDn
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
‘–3’ Speed
2.5
2.8
2.5
2.8
0.0
0.0
4.0
4.6
9.2
9.9
, t
CO
CCA
+ t
7.34
108
100
2.8
3.2
3.7
4.2
6.1
4.6
5.0
5.3
6.8
1.0
1.0
3.6
4.2
3.7
4.1
RD1
= 3.0V, T
+ t
v6.1
10.2
11.0
‘–2’ Speed
PDn
2.7
3.1
2.7
3.1
0.0
0.0
4.4
5.2
, or t
J
= 70°C)
4.6
PD1
3.1
3.5
4.1
4.6
6.8
5.1
5.6
5.9
7.6
1.2
1.2
4.0
4.6
4.2
8.2
98
91
+ t
RD1
11.1
12.0
‘–1’ Speed
3.1
3.5
3.1
3.5
0.0
0.0
5.0
5.9
+ t
SUD
3.5
4.1
4.7
5.3
7.7
5.7
6.3
6.7
8.6
1.3
1.3
4.5
5.2
4.7
5.2
9.3
90
83
, whichever is appropriate.
‘Std’ Speed
12.7
13.8
3.6
4.1
3.6
4.1
0.0
0.0
5.9
6.9
40MX and 42MX FPGA Families
10.1
10.9
4.1
4.8
5.5
6.2
9.0
6.7
7.4
7.8
1.5
1.5
5.3
6.2
5.5
6.1
79
73
21.2
23.0
‘–F’ Speed
5.1
5.7
5.1
5.7
0.0
0.0
8.2
9.6
12.6
10.3
11.0
14.1
15.3
5.7
6.7
7.7
8.7
9.3
2.2
2.2
7.4
8.6
7.7
8.5
47
44
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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