A42MX09-PQG100 Actel, A42MX09-PQG100 Datasheet - Page 17

• Manufacturer Part Number: A42MX09-PQG100
• Description: FPGA - Field Programmable Gate Array 14K System Gates
• Manufacturer: Actel

Specifications of A42MX09-PQG100

• Processor Series: A42MX09
• Core: IP Core
• Number Of Macrocells: 336
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 104
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 14 K
• Package / Case: PQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Each I/O cell has three boundary-scan register cells, each
with a serial-in, serial-out, parallel-in, and parallel-out
pin. The serial pins are used to serially connect all the
boundary-scan register cells in a device into a boundary-
scan register chain, which starts at the TDI pin and ends
Figure 1-14 • 42MX IEEE 1149.1 Boundary Scan Circuitry
Table 3 •
Table 4 •
Port
TMS
Select)
TCK (Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge
TDI (Test Data Input)
TDO
Output)
Instruction
EXTEST
SAMPLE/PRELOAD
HIGH Z
CLAMP
BYPASS
(Test
(Test
Test Access Port Descriptions
Supported BST Public Instructions
TMS
TCK
Mode
TDI
Data
JTAG
JTAG
Description
Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK).
of the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequency
for TCK is 20 MHz.
Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock.
Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (high
impedance) when data scanning is not in progress.
IR Code (IR2.IR0)
000
001
101
110
111
TAP Controller
Instruction
Register
Control Logic
Boundary Scan Register
Instruction Type
Mandatory
Mandatory
Mandatory
Optional
Optional
Instruction
Decode
v6.1
at the TDO pin. The parallel ports are connected to the
internal core logic tile and the input, output and control
ports of an I/O buffer to capture and load data into the
register to control or observe the logic state of each I/O.
Allows the external circuitry and board-level interconnections to
be tested by forcing a test pattern at the output pins and
capturing test results at the input pins.
Allows a snapshot of the signals at the device pins to be
captured and examined during operation
Tristates all I/Os to allow external signals to drive pins. Please
refer to the IEEE Standard 1149.1 specification.
Allows state of signals driven from component pins to be
determined from the Boundary-Scan Register. Please refer to
the IEEE Standard 1149.1 specification for details.
Enables the bypass register between the TDI and TDO pins. The
test data passes through the selected device to adjacent devices
in the test chain.
Register
Bypass
Description
Output
MUX
40MX and 42MX FPGA Families
TDO
1-11