A42MX09-PQG100 Actel, A42MX09-PQG100 Datasheet - Page 14

• Manufacturer Part Number: A42MX09-PQG100
• Description: FPGA - Field Programmable Gate Array 14K System Gates
• Manufacturer: Actel

Specifications of A42MX09-PQG100

• Processor Series: A42MX09
• Core: IP Core
• Number Of Macrocells: 336
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 104
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 14 K
• Package / Case: PQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Dissipation
The general power consumption of MX devices is made
up of static and dynamic power and can be expressed
with the following equation:
General Power Equation
P = [I
where:
Accurate values for N and M are difficult to determine
because they depend on the family type, on design
details, and on the system I/O. The power can be divided
into two components: static and active.
Static Power Component
The static power due to standby current is typically a
small component of the overall power consumption.
Standby power is calculated for commercial, worst-case
conditions. The static power dissipation by TTL loads
depends on the number of outputs driving, and on the
DC load current. For instance, a 32-bit bus sinking 4mA at
0.33V will generate 42mW with all outputs driving LOW,
and 140mW with all outputs driving HIGH. The actual
dissipation will average somewhere in between, as I/Os
switch states with time.
Active Power Component
Power dissipation in CMOS devices is usually dominated
by the dynamic power dissipation. Dynamic power
consumption is frequency-dependent and is a function of
the logic and the external I/O. Active power dissipation
results from charging internal chip capacitances of the
interconnect, unprogrammed antifuses, module inputs,
and module outputs, plus external capacitances due to
PC board traces and load device inputs. An additional
component of the active power dissipation is the totem
pole current in the CMOS transistor pairs. The net effect
can be associated with an equivalent capacitance that
can be combined with frequency and voltage to
represent active power dissipation.
1 -8
40MX and 42MX FPGA Families
I
outputs are changing.
I
switching.
I
V
N equals the number of outputs driving TTL loads to
V
M equals the number of outputs driving TTL loads to
V
CC
CC
OL
OL
OL
OH
standby is the current flowing when no inputs or
active is the current flowing due to CMOS
, I
, V
.
CC
.
OH
standby + I
OH
are TTL sink/source currents.
are TTL level output voltages.
+ I
OH
* (V
CC
active] * V
CCI
– V
OH
) * M
CCI
+ I
OL
* V
OL
* N
v6.1
The power dissipated by a CMOS circuit can be expressed
by the equation:
where:
C
V
F =Switching frequency in megahertz (MHz)
Equivalent Capacitance
Equivalent capacitance is calculated by measuring
I
circuit component of interest. Measurements have been
made over a range of frequencies at a fixed value of
Equivalent capacitance is frequency-independent, so the
results can be used over a wide range of operating
conditions. Equivalent capacitance values are shown
below.
C
Modules (C
Input Buffers (C
Output Buffers (C
Routed Array Clock Buffer Loads (C
To calculate the active power dissipated from the
complete design, the switching frequency of each part of
the logic must be known. The equation below shows a
piece-wise linear summation over all components.
where:
m
n
p
q
q
r
r
CC
1
2
EQ
1
2
CCA
EQ
active at a specified frequency and voltage for each
=Equivalent capacitance expressed in picofarads (pF)
(n *
0.5 * (q
0.5 * (q
Power = V
=Power supply in volts (V)
Values for Actel MX FPGAs
= Number
= Number
= Number
= Number of clock loads on the first routed array
= Number of clock loads on the second routed
= Fixed capacitance due to first routed array
= Fixed capacitance due to second routed array
frequency f
frequency f
frequency f
clock
array clock
clock
clock
Power (µW) = C
C
EQM
EQI
1
2
)3.5
EQI
* f
CCA
*
*
EQO
f
)6.9
C
C
2
of
n
f
q2
of
of
EQCR
EQCR
m
n
p
)
q1
* [(m x
)18.2
)
Inputs
f
)
routed_Clk2
p
routed_Clk1
output
)
logic
input
* f
* f
outputs
EQ
+ (p * (
q1
q2
* V
C
)
)
modules
EQM
routed_Clk1
routed_Clk2
buffers
buffers
+
CCA
(2)
EQCR
+
* f
2
C
* F(1)
)1.4
EQO
m
)
switching
Modules
switching
switching
+ (r
+ (r
+ C
L
) *
1
2
+
*
*
V
CC
at
at
at
.