LFE2M35E-5FN484C Lattice, LFE2M35E-5FN484C Datasheet - Page 27
![FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -5 Spd](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M35E-5FN484C
Manufacturer Part Number
LFE2M35E-5FN484C
Description
FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M35E-5FN484C
Number Of Macrocells
34000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
303
Data Ram Size
2151424
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M35E-5FN484C
Manufacturer:
Lattice
Quantity:
135
Company:
Part Number:
LFE2M35E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
MAC sysDSP Element
In this case, the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers, but the out-
put register is always enabled. The output register is used to store the accumulated value. The Accumulators in the
DSP blocks in the LatticeECP2/M family can be initialized dynamically. A registered overflow signal is also avail-
able. The overflow conditions are provided later in this document. Figure 2-24 shows the MAC sysDSP element.
Figure 2-24. MAC sysDSP
Multiplicand
Multiplier
Signed A
Signed B
Addn
Accumsload
Serial Register B in
n
Input Data
Register B
n
n
SROB
n
Register
Register
Register
Register
Input
Input
Input
Input
m
Input Data
Register A
m
n
SROA
Serial Register A in
m
Register
Register
Register
Register
Pipeline
Pipeline
Pipeline
Pipeline
m
n
2-24
To Accumulator
To Accumulator
To Accumulator
To Accumulator
Multiplier
Register
Pipeline
x
(default)
m+n
Accumulator
LatticeECP2/M Family Data Sheet
CLK (CLK0,CLK1,CLK2,CLK3)
RST(RST0,RST1,RST2,RST3)
CE (CE0,CE1,CE2,CE3)
m+n+16
(default)
Preload
(default)
m+n+16
Architecture
Output
Overflow
signal
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