LFE2M35E-5FN484C Lattice, LFE2M35E-5FN484C Datasheet - Page 16
![FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -5 Spd](/photos/16/14/161499/landingpagelatticeecp2m_sml.jpg)
LFE2M35E-5FN484C
Manufacturer Part Number
LFE2M35E-5FN484C
Description
FPGA - Field Programmable Gate Array 34K LUTs SERDES MEM DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFE2-12SE-6FN256C.pdf
(389 pages)
Specifications of LFE2M35E-5FN484C
Number Of Macrocells
34000
Maximum Operating Frequency
311 MHz
Number Of Programmable I/os
303
Data Ram Size
2151424
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M35E-5FN484C
Manufacturer:
Lattice
Quantity:
135
Company:
Part Number:
LFE2M35E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Secondary Clock/Control Sources
LatticeECP2/M devices derive secondary clocks (SC0 through SC7) from eight dedicated clock input pads and the
rest from routing. Figure 2-11 shows the secondary clock sources.
Figure 2-11. Secondary Clock Sources
Clock Input
Clock Input
From Routing
From Routing
From Routing
From Routing
Routing
Routing
From
From
Routing
Routing
From
From
Secondary Clock Sources
Clock
Clock
Input
Input
2-13
Clock
Clock
Input
Input
Routing
Routing
From
From
LatticeECP2/M Family Data Sheet
Routing
Routing
From
From
From Routing
From Routing
From Routing
From Routing
Clock Input
Clock Input
Architecture
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