APA150-TQG100 Actel, APA150-TQG100 Datasheet - Page 40

• Manufacturer Part Number: APA150-TQG100
• Description: FPGA - Field Programmable Gate Array 150K System Gates
• Manufacturer: Actel

Specifications of APA150-TQG100

• Processor Series: APA150
• Core: IP Core
• Maximum Operating Frequency: 150 MHz
• Number Of Programmable I/os: 242
• Data Ram Size: 36864
• Supply Voltage (max): 2.7 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: APA-Eval-Kit, APA-Eval-BRD1, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 2.3 V
• Number Of Gates: 150 K
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles.
This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as
follows:
P
P
P
P
=> P
P
=> P
P
=> P
P
=> 361 mW
P
P
2 -3 0
=> P
=> P
=> P
clock
storage
logic
outputs
inputs
memory
dc
ac
total
ProASIC
+ P
ms
mc
C
V
Fp
N
Fs
R
q
Fq
p
outputs
inputs
memory
load
DDP
memory
clock
storage
logic
ac
= 374 mW (typical)
= 10 MHz
= 13,440
PLUS
= 0 (no logic tiles in this shift register)
= 0 mW
= (P1 + (P2*R) - (P7*R
= 13,440 (in a shift register 100% of storage tiles are toggling at each clock cycle and Fs = 10 MHz)
= P8 * q * Fq = 0.3 mW
=
=
=
=
= (P4 + (C
= P5 * ms * Fs = 147.8 mW
= 0 mW
=
=
Flash Family FPGAs
40 pF
3.3 V
24
5 MHz
=
1
10 MHz
0 (no RAM/FIFO blocks in this shift register)
load
* V
DDP
2
2
)) * Fs = 121.5 mW
)) * p * Fp = 91.4 mW
v5.9