A3P400-PQG208 Actel, A3P400-PQG208 Datasheet - Page 81
![no-image](/images/manufacturer_photos/0/0/8/actel_sml.jpg)
A3P400-PQG208
Manufacturer Part Number
A3P400-PQG208
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P400-PQG208
Processor Series
A3P400
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
194
Data Ram Size
55296
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P400-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
- Current page: 81 of 218
- Download datasheet (7Mb)
Figure 2-11 • LVDS Circuit Diagram and Board-Level Implementation
OUTBUF_LVDS
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the
user instantiates a differential I/O macro in the design.
Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output
Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no
support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It
requires that one data bit be carried through two signal lines, so two pins are needed. It also requires
external resistor termination.
The full implementation of the LVDS transmitter and receiver is shown in an example in
building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three
board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver
resistors are different from those used in the LVPECL implementation because the output standard
specifications are different.
Along with LVDS I/O, ProASIC3 also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)
configuration (up to 40 nodes).
FPGA
P
N
Bourns Part Number: CAT16-LV4F12
165 Ω
165 Ω
140 Ω
R e v i s i o n 9
Z
Z
0
0
= 50 Ω
= 50 Ω
100 Ω
N
P
FPGA
ProASIC3 Flash Family FPGAs
+
–
Figure
INBUF_LVDS
2-11. The
2- 67
Related parts for A3P400-PQG208
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![A3P400-FG144I](/images/manufacturer_photos/0/0/8/actel_tmb.jpg)
Part Number:
Description:
A3P400-FG144I
Manufacturer:
Actel
Datasheet:
![A3P400-FGG144I](/images/manufacturer_photos/0/0/8/actel_tmb.jpg)
Part Number:
Description:
FBGA 144/I°/A3P400-FGG144I
Manufacturer:
Actel
Datasheet:
![A3P400-FGG144](/images/manufacturer_photos/0/0/8/actel_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer:
Actel
Datasheet:
![A3P400-FGG484](/images/manufacturer_photos/0/0/8/actel_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer:
Actel
Datasheet:
![A3P400-FGG256](/images/manufacturer_photos/0/0/8/actel_tmb.jpg)
Part Number:
Description:
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer:
Actel
Datasheet:
![A3P400-1PQG208I](/images/manufacturer_photos/0/0/8/actel_tmb.jpg)
Part Number:
Description:
PQFP 208/FPGA, 9216 CLBS, 400000 GATES, 350 MHz
Manufacturer:
Actel
![A3P400-2FG144I](/images/manufacturer_photos/0/0/8/actel_tmb.jpg)
Part Number:
Description:
BGA 144/IC,FPGA,9216-CELL,CMOS
Manufacturer:
Actel
Datasheet: