A3P400-PQG208 Actel, A3P400-PQG208 Datasheet - Page 21
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A3P400-PQG208
Manufacturer Part Number
A3P400-PQG208
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P400-PQG208
Processor Series
A3P400
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
194
Data Ram Size
55296
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P400-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
3.3 V PCI
3.3 V PCI-X
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
specification.
specification.
Applicable to Standard Plus I/O Banks
Applicable to Standard I/O Banks
3
3
VMV (V)
R e v i s i o n 9
VMV (V)
3.3
3.3
2.5
1.8
1.5
3.3
3.3
3.3
3.3
2.5
1.8
1.5
Static Power
P
Static Power
P
DC2
DC2
(mW)
–
–
–
–
–
–
–
(mW)
–
–
–
–
–
1
1
ProASIC3 Flash Family FPGAs
P
P
Dynamic Power
Dynamic Power
AC9
AC9
(µW/MHz)
16.23
16.23
18.13
18.13
(µW/MHz)
17.24
17.24
5.14
2.13
1.48
5.19
2.18
1.52
2
2
2 -7
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