A3P400-PQG208 Actel, A3P400-PQG208 Datasheet - Page 209
![no-image](/images/manufacturer_photos/0/0/8/actel_sml.jpg)
A3P400-PQG208
Manufacturer Part Number
A3P400-PQG208
Description
FPGA - Field Programmable Gate Array 400K System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P400-PQG208
Processor Series
A3P400
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
194
Data Ram Size
55296
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
400 K
Package / Case
PQFP-208
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P400-PQG208I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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Revision
Revision 2 (Feb 2008)
Product Brief v1.0
Packaging v1.2
Revision 1 (Feb 2008)
DC
Characteristics v1.1
Packaging v1.1
Revision 0 (Jan 2008) This document was previously in datasheet v2.2. As a result of moving to the
v2.2
(July 2007)
and
Switching
The
This document was divided into two sections and given a version number, starting
at v1.0. The first section of the document includes features, benefits, ordering
information, and temperature and speed grade offerings. The second section is a
device family overview.
This document was updated to include A3P015 device information. QN68 is a
new package that was added because it is offered in the A3P015. The following
sections were updated:
"Features and Benefits"
"ProASIC3 Ordering Information"
"Temperature Grade Offerings"
"ProASIC3 Product Family"
"A3P015 and A3P030"
"Introduction and Overview"
The
In the
updated to include both 0.4 mm and 0.5 mm.
In the
300.
In
symbol column and was incorrect. It was corrected and changed to T
In
Temperature1, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
The
In the
FCLKIN is the input clock frequency.
In
was incorrect. It previously said T
In
1 are new.
in the previous version of the document.
In the
changed from IO39RSB0 to GDB0/IO38RSB0.
handbook format, Actel has restarted the version numbers.
The M7 and M1 device part numbers have been updated in Table 1 • ProASIC3
Product Family, "I/Os Per Package", "Automotive ProASIC3 Ordering
Information",
Temperature Grade Matrix".
The words "ambient temperature" were added to the temperature range in the
"Automotive ProASIC3 Ordering Information", "Temperature Grade Offerings",
and "Speed Grade and Temperature Grade Matrix" sections.
Table 2-125 • JTAG 1532
Table 2-115 • ProASIC3 CCC/PLL
Table 2-21 • Summary of Maximum and Minimum DC Input
Table 2-3 • Flash Programming Limits – Retention, Storage and Operating
Table 2-2 • Recommended Operating Conditions
"ProASIC3 FPGAs Package Sizes Dimensions"
"68-Pin QFN" section
"PLL Behavior at Brownout Condition" section
"General Description"
"PLL Contribution—PPLL"
"100-Pin VQFP"
"ProASIC3 Ordering
"Temperature
A3P030 pin table, the function of pin 63 was incorrect and
note
is new.
was populated with the parameter data, which was not
section, the number of I/Os was updated from 288 to
Information", the QN package measurements were
Grade
section, the following was deleted:
J
R e v i s i o n 9
and it was corrected and changed to T
Changes
Specification, the SCLK parameter and note
Offerings",
is new.
and
table is new.
1,2
, T
"Speed
J
was listed in the
Levels, the note
ProASIC3 Flash Family FPGAs
Grade
A
.
A
.
and
i, ii, iii,
2-112
Page
2-13
2-21
2-92
3-19
iii, iv
iii, iv
N/A
N/A
N/A
1-1
3-3
2-2
2-2
2-3
III
II
4 -3
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