LFXP20C-3FN256C Lattice, LFXP20C-3FN256C Datasheet - Page 344

• Manufacturer Part Number: LFXP20C-3FN256C
• Description: FPGA - Field Programmable Gate Array 19.7K LUTS 188 I/O
• Manufacturer: Lattice

Specifications of LFXP20C-3FN256C

• Number Of Programmable I/os: 188
• Data Ram Size: 405504
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
In the Synplicity
value to 1000 instead of using the default value of 100. This will guide the tool to allow high fanout signals without
replicating the logic. In the LeonardoSpectrum tool project GUI, under Technology => Advanced Settings, users
can set the Max Fanout to be any number instead of the default value “0”.
Use ispLEVER Project Navigator Results for Device Utilization and Performance
Many synthesis tools give usage reports at the end of a successful synthesis. These reports show the name and
the number of library elements used in the design. The data in these reports do not represent the actual implemen-
tation of the design in the final Place and Route tool because the EDIF netlist will be further optimized during Map-
ping and Place and Route to achieve the best results. It is strongly recommended to use the MAP report and the
PAR report in the ispLEVER Project Navigator tool to understand the actual resource utilization in the device.
Although the synthesis report also provides a performance summary, the timing information is based on estimated
logic delays only. The Place & Route TRACE Report in the ispLEVER Project Navigator gives accurate perfor-
mance analysis of the design by including actual logic and routing delays in the paths.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
e-mail:
Internet:
[phone] (Outside North America)
[e-mail]
www.latticesemi.com
®
project GUI, under the Implementation Options => Devices tab, users can set the Fanout Guide
13-17
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs