A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 75

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Conditioning Circuits
Table 2-84 • SmartFusion CCC/PLL Specification
Note:
Figure 2-28 • Peak-to-Peak Jitter Definition
Parameter
Clock Conditioning Circuitry Input Frequency f
Clock Conditioning Circuitry Output Frequency f
Delay Increments in Programmable Delay Blocks
Number of Programmable Values in Each Programmable
Delay Block
Input Period Jitter
CCC Output Peak-to-Peak Period Jitter F
Acquisition Time
Tracking Jitter
Output Duty Cycle
Delay Range in Block: Programmable Delay 1
Delay Range in Block: Programmable Delay 2
Delay Range in Block: Fixed Delay
Notes:
1. One of the CCC outputs (GLA0) is used as an MSS clock and is limited to 100 MHz (maximum) by software. Details
2. This delay is a function of voltage and temperature. See
3. T
4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
regarding CCC/PLL are in the "PLLs, Clock Conditioning Circuitry, and On-Chip Crystal Oscillators" chapter of the
SmartFusion Microcontroller Subsystem User's
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
0.75 MHz to 24 MHz
24 MHz to 100 MHz
100 MHz to 250 MHz
250 MHz to 350 MHz
LockControl = 0
LockControl = 1
LockControl = 0
LockControl = 1
J
= 25°C, VCC = 1.5 V
Peak-to-peak jitter measurements are defined by T
Output Signal
CCC Electrical Specifications
Timing Characteristics
4
2,3
CCC_OUT
IN_CCC
2,3
2,3
OUT_CCC
Guide.
2, 3
T
period_max
peak-to-peak
Table 2-7 on page 2-9
R e v i s i o n 6
Minimum
1 Global
Network
0.50%
1.00%
1.75%
2.50%
0.025
Used
0.75
48.5
1.5
0.6
= T
period_max
T
SmartFusion Intelligent Mixed Signal FPGAs
period_min
Max Peak-to-Peak Period Jitter
Typical
for deratings.
160
2.2
– T
period_min
Maximum
Networks
3 Global
0.70%
1.20%
2.00%
5.60%
Used
350
5.15
5.56
5.56
.
350
300
1.5
6.0
1.6
0.8
32
1
Units
MHz
MHz
ms
ps
ns
µs
ns
ns
ns
ns
ns
%
2- 63