A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 31

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

User I/O Characteristics
Figure 2-2 • Timing Model
(Applicable
I/O Bank,
EMC pin)
FPGA I/O Bank,
t
to FPGA
PY
LVPECL
(Applicable for
= 0.81 ns (FPGA I/O Bank, EMC pin)
EMC pin)
Clock
M-LVDS
Input LVTTL
BLVDS,
LVDS,
Timing Model
Operating Conditions: –1 Speed, Commercial Temperature Range (T
Worst Case VCC = 1.425 V
t
PY
(Non-Registered)
(Registered)
= 1.46 ns
t
I/O Module
I/O Module
t
t
PY
ICLKQ
ISUD
= 1.55 ns
= 0.27 ns
= 0.24 ns
D
Q
Register Cell
t
t
CLKQ
SUD
D
= 0.44 ns
= 0.56 ns
(FPGA I/O Bank, EMC pin)
Combinational Cell
Q
Combinational Cell
t
PD
Combinational Cell
t
PD
Clock
Input LVTTL
t
PY
= 0.89 ns
t
= 0.57 ns
PD
= 0.81 ns
= 0.48 ns
Combinational Cell
Combinational Cell
Y
Y
t
PD
t
PD
Y
= 0.51 ns
= 0.48 ns
Register Cell
Combinational Cell
t
t
R e v i s i o n 6
CLKQ
SUD
D
t
PD
(FPGA I/O Bank, EMC pin)
Y
Y
= 0.44 ns
(Non-Registered)
= 0.56 ns
= 0.49 ns
t
Q
I/O Module
DP
Clock
t
Input LVTTL
PY
= 2.81 ns (FPGA I/O Bank, EMC pin)
(Non-Registered)
(Non-Registered)
t
t
DP
I/O Module
I/O Module
DP
= 0.81 ns
Y
= 4.13 ns (FPGA I/O Bank, EMC pin)
= 3.87 ns (FPGA I/O Bank, EMC pin)
(Non-Registered)
SmartFusion Intelligent Mixed Signal FPGAs
t
I/O Module
DP
LVTTL Output drive strength = 12 mA
= 1.53 ns
t
t
D
OCLKQ
OSUD
(Registered)
I/O Module
LVTTL Output drive strength = 8 mA
LVCMOS 1.5 V Output drive strength = 4 mA
High slew rate
Q
= 0.32 ns
= 0.60 ns
t
(FPGA I/O Bank, EMC pin)
DP
High slew rate
= 2.81 ns
LVPECL (applicable to
FPGA /O bank, EMC pin)
J
= 85°C),
High slew rate
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
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