A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 62

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
Figure 2-18 • Output Enable Register Timing Diagram
Table 2-72 • Output Enable Register Propagation Delays
2- 50
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Enable
CLK
D_Enable
Preset
EOUT
Clear
OECLKQ
OESUD
OEHD
OESUE
OEHE
OECLR2Q
OEPRE2Q
OEREMCLR
OERECCLR
OEREMPRE
OERECPRE
OEWCLR
OEWPRE
OECKMPWH
OECKMPWL
For specific junction temperature and voltage supply levels, refer to
Worst Commercial-Case Conditions: T
Output Enable Register
Timing Characteristics
50%
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Enable Setup Time for the Output Enable Register
Enable Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
Clock Minimum Pulse Width High for the Output Enable Register
Clock Minimum Pulse Width Low for the Output Enable Register
50%
t
OESUE
1
t
OEHE
50%
t
OESUD
50%
t
0
OECLKQ
t
50%
OEHD
50%
50%
t
OEWPRE
Description
t
OEPRE2Q
50%
50%
J
= 85°C, Worst-Case VCC = 1.425 V
t
50%
OERECPRE
R e visio n 6
50%
t
t
OEWCLR
OECLR2Q
50%
50%
Table 2-7 on page 2-9
t
50%
OERECCLR
50%
t
OECKMPWH
t
OEREMPRE
50%
0.45
0.32
0.00
0.44
0.00
0.68
0.68
0.00
0.23
0.00
0.23
0.22
0.22
0.36
0.32
for derating values.
–1
50%
t
OECKMPWL
0.54
0.38
0.00
0.53
0.00
0.81
0.81
0.00
0.27
0.00
0.27
0.22
0.22
0.36
0.32
Std.
t
OEREMCLR
50%
50%
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns