MAX5978ETJ+ Maxim Integrated Products, MAX5978ETJ+ Datasheet - Page 25

• Manufacturer Part Number: MAX5978ETJ+
• Description: Hot Swap & Power Distribution 0-16V HOTSWAP CONTLR W/10BIT CUR VOLT MON
• Manufacturer: Maxim Integrated Products

Specifications of MAX5978ETJ+

• Product: Controllers & Switches
• Supply Voltage (max): 16 V
• Supply Voltage (min): 0 V
• Power Dissipation: 2759 mW
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Supply Current: 2.5 mA
• Package / Case: TQFN-32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 27. Overvoltage Critical Threshold Register Format (Low-Order Bits)
Table 28. PROT Input and prot[] Bits
Table 29. status3 Register Format
Table 30a. Power-Good Assertion Delay-Time Register Format
Table 30b. Power-Good Assertion Delay
The PG output is asserted when the voltage at MON is
between the undervoltage and overvoltage critical limits.
The status of the power-good signal is maintained in
register status3[0]. A value of 1 in the pg[] bit indicates
Description:
Register Title:
Register Addresses:
Description:
Register Title:
Register Address:
Description:
Register Title:
Register Address:
pgdly1
PROT INPUT
Unconnected
Bit 7
Bit 7
Bit 7
0
0
1
1
—
STATE
—
—
R
R
R
High
Low
Power-Good Detection and PG Output
Current, Voltage Monitor, and 4 LED Drivers
pgdly0
0 to 16V, Hot-Swap Controller with 10-Bit
0
1
0
1
Bit 6
Bit 6
Bit 6
—
—
—
R
R
R
prot[1]
0
0
1
PG ASSERTION DELAY (ms)
Overvoltage critical threshold low-order bits [1:0]
ov2thr_lsb
0x21
Power-good status register: POL, ALERT, and power-good bits
status3
0x34
Power-good assertion delay-time register
pgdly
0x38
Bit 5
Bit 5
Bit 5
POL
prot[0]
—
—
R
R
R
0
1
0
100
200
400
50
UV/OV WARNING
ALERT
Bit 4
Bit 4
R/W
Bit 4
Assert ALERT
Assert ALERT
Assert ALERT
—
—
R
R
ACTION
Unused
Bit 3
Bit 3
R/W
Bit 3
—
—
R
R
a power-good condition, regardless of the POL setting,
which only affects the PG output pin polarity. The open-
drain PG output can be configured for active-high or
active-low status indication by the state of the POL input
(see Table 29).
The POL input sets the value of status3[5], which is a
read-only bit; the state of the POL input can be changed
at any time during operation and the polarity of the PG
output changes accordingly.
The assertion of the PG output is delayed by a user-
selectable time delay of 50ms, 100ms, 200ms, or 400ms
(see Tables 30a and 30b).
Assert ALERT, clear PG, shut down channel
Assert ALERT, clear PG
Assert ALERT
Unused
Bit 2
Bit 2
Bit 2
R/W
R/W
—
—
R
UV/OV CRITICAL ACTION
Unused
pgdly1
ov2_1
R/W
Bit 1
Bit 1
R/W
Bit 1
R
pgdly0
ov2_0
pg[0]
Bit 0
Bit 0
Bit 0
R/W
R/W
R
RESET
VALUE
RESET
VALUE
RESET
VALUE
0x03
0x00
—
—
—
—
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