PIC18F6585-I/L Microchip Technology, PIC18F6585-I/L Datasheet - Page 36

• Manufacturer Part Number: PIC18F6585-I/L
• Description: Microcontrollers (MCU) 48KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6585-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 48 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
3.1
A Power-on Reset pulse is generated on-chip when
V
cuitry, tie the MCLR pin through a 1 k
tor to V
usually needed to create a Power-on Reset delay. A
minimum rise rate for V
D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 3-2:
3.2
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in Reset as long as the PWRT is active.
The PWRT’s time delay allows V
acceptable level. A configuration bit is provided to
enable/disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to V
parameter #33 for details.
DS30491C-page 34
DD
Note 1: External Power-on Reset circuit is required
DD
rise is detected. To take advantage of the POR cir-
, temperature and process variation. See DC
DD
Power-on Reset (POR)
Power-up Timer (PWRT)
2: R < 40 k is recommended to make sure that
3: R1 = 1 k to 10 k will limit any current flow-
. This will eliminate external RC components
D
only if the V
The diode D helps discharge the capacitor
quickly when V
the voltage drop across R does not violate
the device’s electrical specification.
ing into MCLR from external capacitor C, in
the event of MCLR/V
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
V
DD
R
C
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD
R1
DD
DD
power-up slope is too slow.
powers down.
is specified (parameter
PP
DD
PIC18FXX8X
MCLR
pin breakdown due to
POWER-UP)
DD
to 10 k resis-
to rise to an
3.3
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
Sleep.
3.4
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(T
start-up time-out (OST).
3.5
A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If V
than parameter #35, the brown-out situation will reset
the chip. A Reset may not occur if V
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until V
BV
invoked after V
the chip in Reset for an additional time delay (parame-
ter #33). If V
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
V
execute the additional time delay.
3.6
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, the
time-outs will expire if MCLR is kept low long enough.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18FXX8X device
operating in parallel.
Table 3-2 shows the Reset conditions for some Special
Function Registers while Table 3-3 shows the Reset
conditions for all of the registers.
DD
PLL
DD
) is typically 2 ms and follows the oscillator
. If the Power-up Timer is enabled, it will be
rises above BV
Oscillator Start-up Timer (OST)
PLL Lock Time-out
Brown-out Reset (BOR)
Time-out Sequence
DD
DD
DD
falls below parameter D005 for greater
drops below BV
rises above BV
DD
 2004 Microchip Technology Inc.
, the Power-up Timer will
DD
DD
while the Power-up
; it then will keep
DD
DD
rises above
falls below