PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 9

• Manufacturer Part Number: PI7C21P100BNHE
• Description: Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BNHE

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: CSBGA-304
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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DESCRIPTION
The PI7C21P100B is a 2-port PCI-X 2.0 Bridge designed to be compliant with the PCI-X
Addendum to the Local Bus Specification Revision 1.0a. The PI7C21P100B is able to handle
64-bit data at a maximum bus frequency of 133MHz. The PI7C21P100B is designed for high
speed applications such as Ethernet, SCSI, and Fibre Channel. The PI7C21P100B may also
be used for bus expansion, frequency isolations/translations, or PCI-X to PCI
isolations/translations.
FEATURES
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INDUSTRY STANDARDS COMPLIANCE
INTERFACE
OPERATION
ADDITIONAL FEATURES
PACKAGING
PCI-X Addendum to the Local Bus Specification Revision 1.0a (Mode 1 only)
PCI Local Bus Specification Revision 2.2
PCI-to-PCI Bridge Architecture Specification Revision 1.1
PCI Power Management Interface Specification Revision 1.1
3.3V signaling
133MHz / 64-bit operation on both buses
Dual address cycle support
Concurrent primary and secondary bus operation
Primary and secondary may be run in either PCI mode or PCI-X Mode 1
Asynchronous operation support
Programmable internal arbiter with support for up to 6 external masters on the
secondary bus
IEEE 1149.1 JTAG support
Type 0 and Type 1 configuration support
Configuration register access from both primary and secondary buses
2KB of buffering for upstream memory burst read commands
2KB of buffering for downstream memory burst read commands
1KB of buffering for upstream posted memory write commands
1KB of buffering for downstream posted memory write commands
Support for up to 8 active transactions in each direction
Capabilities pointer
Ability to define an opaque memory address
Definable base address register
Secondary side PCI-X device privatization
304-pin PBGA, 31 x 31 mm
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Supports D0 and D3 power states
Internal arbiter may be disabled to use an external arbiter
Page 9 of 79
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B