PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 46

• Manufacturer Part Number: PI7C21P100BNHE
• Description: Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BNHE

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: CSBGA-304
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1.12
8.1.13
8.1.14
8.1.15
8.1.16
8.1.17
LOWER MEMORY BASE ADDRESS REGISTER – OFFSET 10h
UPPER MEMORY BASE ADDRESS REGISTER – OFFSET 14h
PRIMARY BUS NUMBER REGISTER – OFFSET 18h
SECONDARY BUS NUMBER REGISTER – OFFSET 18h
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
BIT
31:20
19:4
3
2:1
0
BIT
31:0
BIT
7:0
BIT
15:8
BIT
23:16
BIT
31:24
FUNCTION
Memory Base Address
Reserved
Prefetchable Indicator
Decoder Width
Decoder Type
FUNCTION
Upper Memory Base
Address
FUNCTION
Primary Bus Number
FUNCTION
Secondary Bus Number
FUNCTION
Subordinate Bus
Number
FUNCTION
Secondary Latency
Timer
TYPE
TYPE
TYPE
RW
TYPE
TYPE
TYPE
RW
RO
RO
RO
RO
RW
RW
RW
RW
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DESCRIPTION
Address bits[31:20] of the memory base address if BAR_EN is 1. If
BAR_EN is 0, then this register is reserved and returns zeros when
read.
Reserved. Returns 00h when read
Identifies the address range defined by this register is prefetchable.
Returns 1 when read
Indicates that this is the lower portion of a 64-bit register. Returns
10b when read.
Indicates that this register is a memory decoder. Returns 0 when
read.
DESCRIPTION
Address bits[63:32] of the memory base address if BAR_EN is 1. If
BAR_EN is 0, this register is reserved and returns zeros when read.
DESCRIPTION
Records the bus number of the PCI segment that PI7C21P100B is
connected to on the primary side.
Reset to 00h
DESCRIPTION
Records the bus number of the PCI segment that PI7C21P100B is
connected to on the secondary side.
Reset to 00h
DESCRIPTION
Records the highest bus number of the PCI segment that resides
behind PI7C21P100B.
Reset to 00h
DESCRIPTION
Specifies the value of the secondary latency timer in PCI bus clock
units.
Reset to 00h in conventional PCI mode
Reset to 40h in PCI-X mode
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
PI7C21P100B