PI7C21P100BNHE Pericom Semiconductor, PI7C21P100BNHE Datasheet - Page 60

• Manufacturer Part Number: PI7C21P100BNHE
• Description: Peripheral Drivers & Components (PCIs) PCI-X to PCI-XBridge 2 Port
• Manufacturer: Pericom Semiconductor

Specifications of PI7C21P100BNHE

• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: CSBGA-304
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.1.51
8.1.52
8.1.53
8.1.54
OPAQUE MEMORY LIMIT UPPER 32-BIT REGISTER – OFFSET
7Ch
PCI-X CAPABILITY ID REGISTER – OFFSET 80h
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h
PCI-X SECONDARY STATUS REGISTER – OFFSET 80h
BIT
31:0
BIT
7:0
BIT
15:8
BIT
31:25
24:22
21
20
FUNCTION
Opaque Memory Base
Upper 32-bit Register
FUNCTION
PCI-X Capability ID
FUNCTION
Next Capability Pointer
FUNCTION
RESERVED
Secondary Clock
Frequency
Split Request Delayed
Split Completion
Overrun
TYPE
TYPE
TYPE
RO
TYPE
RO
RW
RW
RO
RO
RW
Page 60 of 79
DESCRIPTION
Opaque Memory Base Upper 32-bit Register
Address bits[63:32] of the opaque memory limit address. In this
range, memory transactions are not accepted by PI7C21P100B on
both primary and secondary interfaces.
Reset to FFFF FFFFh
DESCRIPTION
PCI-X Capability ID
Returns 07h when read to indicate that this register set of the
Capabilities List is a PCI-X register set.
DESCRIPTION
Next Capability Pointer
Returns 90h when read to indicate that there are more list items in the
Capabilities List.
DESCRIPTION
Reserved. Returns 0000000 when read.
Secondary Clock Frequency
Enables the configuration software to determine what mode and what
frequency PI7C21P100B set the secondary bus to the last time the
secondary RST# was asserted.
VALUE
000
001
010
011
1xx
Split Request Delayed
0: The bridge has not delayed a split request
1: The bridge has delayed a split request because the bridge cannot
forward a transaction to the secondary bus because there isn’t enough
room within the limit specified in the split transaction commitment
limit field in the downstream split transaction control register.
Reset to 0
Split Completion Overrun
0: PI7C21P100B has accepted all split completions.
1: PI7C21P100B has terminated a split completion on the secondary
bus with retry or disconnect at the next ADB because the bridge
buffers were full.
Reset to 0
MAX CLOCK FREQUENCY
conventional mode
66 MHz
100 MHz
133 MHz
Reserved
2-PORT PCI-X TO PCI-X BRIDGE
November 2005 – Revision 1.02
MIN CLK PERIOD
N/A
15ns
10ns
7.5ns
Reserved
PI7C21P100B