UJA1061TW/5V0/C/T, NXP Semiconductors, UJA1061TW/5V0/C/T, Datasheet - Page 63

• Manufacturer Part Number: UJA1061TW/5V0/C/T,
• Description: IC CAN/LIN FAIL-SAFE HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW/5V0/C/T,

• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Applications: Automotive Networking
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 2
• Supply Voltage (max): 27 V or 52 V
• Supply Voltage (min): 5.5 V
• Supply Current (max): 10 mA or 25 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935288866518

NXP Semiconductors
Table 27.
T
voltages are defined with respect to ground. Positive currents flow into the IC.
UJA1061_6
Product data sheet
Symbol
t
Δt
LIN transceiver; pins LIN, TXDL and RXDL
δ1
δ2
δ3
δ4
t
t
t
t
t
t
CANH,
p(rx)
p(rx)(sym)
BUS(LIN)
LIN(dom)(det)
LIN(dom)(rec)
TXDL(dom)(dis)
vj
PC
=
−
40
t
CANL
°
C to + 150
Dynamic characteristics
Parameter
ground shift sampling
time required for
CANH, CANL voltage
level
pulse count
difference between
CANH and CANL for
failure detection
dominant pulse count
on CANH and CANL
for failure recovery
duty cycle 1
duty cycle 2
duty cycle 3
duty cycle 4
propagation delay of
receiver
symmetry of receiver
propagation delay
minimum dominant
time for wake-up of
the LIN-transceiver
continuously
dominant clamped
LIN-bus detection
time
continuously
dominant clamped
LIN-bus recovery
time
TXDL permanent
dominant disable time
°
C; V
BAT42
= 5.5 V to 52 V; V
[1]
Conditions
Active mode, On-line and
Selective Sleep mode;
V
bus failures H//, L//, HxGND
and LxVCC; Active mode,
On-line and Selective Sleep
mode; V
bus failures H//, L//, HxGND
and LxVCC; Active mode,
On-line and Selective Sleep
mode; V
V
V
LSC = 0; t
V
V
V
LSC = 0; t
V
V
V
LSC = 1; t
V
V
V
LSC = 1; t
V
C
rising edge with respect to
falling edge; C
Off-line mode
Active mode; LIN = 0 V
Active mode
Active mode; TXDL = 0 V
…continued
V2
th(reces)(max)
th(dom)(max)
BAT42
th(reces)(min)
th(dom)(min)
BAT42
th(reces)(max)
th(dom)(max)
BAT42
th(reces)(min)
th(dom)(min)
BAT42
RXDL
All information provided in this document is subject to legal disclaimers.
= 5 V; TXDC recessive
[3]
= 20 pF
= 7 V to 18 V
= 7.6 V to 18 V
= 7 V to 27 V
= 7.6 V to 27 V
V2
V2
BAT14
bit
bit
bit
bit
Rev. 06 — 9 March 2010
= 5 V
= 5 V
= 0.284 × V
= 0.251 × V
= 0.581 × V
= 0.616 × V
= 50 μs;
= 50 μs;
= 96 μs;
= 96 μs;
= 0.422 × V
= 0.389 × V
= 0.744 × V
= 0.778 × V
RXDL
= 5.5 V to 27 V; V
= 20 pF
BAT42
BAT42
BAT42
BAT42
BAT42
BAT42
BAT42
BAT42
Fault-tolerant CAN/LIN fail-safe system basis chip
;
;
;
;
;
;
;
;
BAT42
[4]
[5]
[4]
[5]
Min
20
-
-
0.396
-
0.417
-
-
−2
30
40
0.8
20
≥
V
BAT14
−
1 V; unless otherwise specified. All
Typ
-
4
4
-
-
-
-
-
-
-
-
-
-
UJA1061
Max
80
-
-
-
0.581
-
0.590
6
+2
150
160
2.2
80
© NXP B.V. 2010. All rights reserved.
Unit
μs
pulses
pulses
μs
μs
μs
ms
ms
ms
63 of 77