UJA1061TW/5V0/C/T, NXP Semiconductors, UJA1061TW/5V0/C/T, Datasheet - Page 19

• Manufacturer Part Number: UJA1061TW/5V0/C/T,
• Description: IC CAN/LIN FAIL-SAFE HS 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1061TW/5V0/C/T,

• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Applications: Automotive Networking
• Interface: CAN, LIN
• Voltage - Supply: 5.5 V ~ 27 V
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 2
• Supply Voltage (max): 27 V or 52 V
• Supply Voltage (min): 5.5 V
• Supply Current (max): 10 mA or 25 mA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935288866518

NXP Semiconductors
UJA1061_6
Product data sheet
6.7.1 Mode control
6.7 CAN transceiver
The integrated fault-tolerant CAN transceiver of the UJA1061 is an advanced ISO11898-3
compliant transceiver and is interoperable with the TJA1054 and TJA1054A stand-alone
transceivers. In addition to standard fault-tolerant CAN transceivers the UJA1061
transceiver provides the following features:
The controller of the CAN transceiver provides four modes of operation: Active mode,
On-line mode, On-line Listen mode and Off-line mode; see
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Enhanced error handling and reporting of bus and RXD/TXD failures; these failures
are separately identified in the System Diagnosis register
Integrated autonomous control system for determining the mode of the CAN
transceiver
Ground shift detection with two selectable warning levels, to detect possible local
ground problems before the CAN communication is affected
On-line Listen mode with global wake-up message filter allows partial networking
Bus connections are truly floating when power is off
All information provided in this document is subject to legal disclaimers.
Rev. 06 — 9 March 2010
Fault-tolerant CAN/LIN fail-safe system basis chip
Figure
8.
UJA1061
© NXP B.V. 2010. All rights reserved.
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