MCIMX253CVM4 Freescale Semiconductor, MCIMX253CVM4 Datasheet - Page 124

• Manufacturer Part Number: MCIMX253CVM4
• Description: IC MPU I.MX25 IND 400MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX25r

Specifications of MCIMX253CVM4

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: External Program Memory
• Ram Size: 144K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.52 V
• Data Converters: A/D 3x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 400-LFBGA
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

3.7.20.2
Table 98
Figure 97
parameters (USB15–USB17) shown in the figure.
4
4.1
Figure 98
124
US15
US16
US17
USB_Data[7:0]
USB_Clk
USB_Stp
USB_Nxt
USB_Dir
•
•
ID
Name
Package Information and Contact Assignment
All dimensions in millimeters.
Dimensioning and tolerancing per ASME Y14.5M-1994.
defines the USB parallel interface signals.
400 MAPBGA—Case 17x17 mm, 0.8 mm Pitch
shows the USB parallel mode transmit/receive waveform.
USB_Dir/Nxt
shows the 17×17 mm i.MX25 production package. The following notes apply to
USB_Data
USB_Clk
USB_Stp
Setup time (Dir&Nxt in, Data in)
Hold time (Dir&Nxt in, Data in)
Output delay time (Stp out, Data out
USB Parallel Interface Timing
Direction
Out
I/O
In
In
In
i.MX25 Applications Processor for Consumer and Industrial Products, Rev. 8
Figure 97. USB Parallel Mode Transmit/Receive Waveform
Interface clock—All interface signals are synchronous to USB_Clk
Bidirectional data bus, driven low by the link during idle—Bus ownership is determined by the
direction
Direction—Control the direction of the data bus
Stop—The link asserts this signal for one clock cycle to stop the data stream currently on the bus
Next—The PHY asserts this signal to throttle the data
US15
Table 98. Signal Definitions for USB Parallel Interface
Table 99. USB Timing Specification in Parallel Mode
US15
Parameter
US16
US16
US17
Signal Description
Min.
—
—
—
Table 99
Max.
6.0
0.0
9.0
US17
describes the timing
Unit
ns
ns
ns
Freescale Semiconductor
Reference Signal
Conditions/
Figure
10 pF
10 pF
10 pF
98: