PK60X256VMD100 Freescale Semiconductor, PK60X256VMD100 Datasheet - Page 62

• Manufacturer Part Number: PK60X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK60X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 100
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Peripheral operating requirements and behaviors
6.8.7 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
62
DSPI_PCSn
DSPI_SCK
(CPOL=0)
DSPI_SIN
DSPI_SOUT
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 44. Master mode DSPI timing (high-speed mode)
Figure 26. DSPI classic SPI timing — master mode
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
DS7
DS3
Description
First data
DS8
First data
DS5
DS2
Preliminary
Data
Data
DS6
(t
(t
(t
SCK
BUS
BUS
2 x t
DS1
Last data
TBD
Min.
2.7
−2
—
—
/2) − 2
2
2
0
x 2) −
x 2) −
BUS
Last data
(t
DS4
SCK
Max.
3.6
8.5
25
—
—
—
—
—
—
/2) + 2
Freescale Semiconductor, Inc.
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
Notes
1
2