PK60X256VMD100 Freescale Semiconductor, PK60X256VMD100 Datasheet - Page 30

• Manufacturer Part Number: PK60X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK60X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 100
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Peripheral operating requirements and behaviors
1. The startup time is defined as the time between the IRC being enabled, either by the MCG or by the IRCLKEN bit being
2. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation
30
f
dco_t_DMX3
t
Symbol
fll_acquire
J
J
t
J
J
f
pll_lock
set, and the first edge of the internal reference clock.
mode).
(Δf
D
acc_pll
pll_ref
cyc_pll
D
cyc_fll
acc_fll
f
I
I
vco
lock
pll
pll
2
unl
dco_t
) over voltage and temperature should be considered.
DCO output
frequency
FLL period jitter
FLL accumulated jitter of DCO output over a 1µs
time window
FLL target frequency acquisition time
VCO operating frequency
PLL operating current
PLL operating current
PLL reference frequency range
PLL period jitter (RMS)
PLL accumulated jitter over 1µs (RMS)
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
Description
• PLL @ 96 MHz (f
• PLL @ 48 MHz (f
• f
• f
• f
• f
2 MHz, VDIV multiplier = 48)
2 MHz, VDIV multiplier = 24)
vco
vco
vco
vco
= 48 MHz
= 100 MHz
= 48 MHz
= 100 MHz
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Table 15. MCG specifications (continued)
Mid-high range (DRS=10)
High range (DRS=11)
Low range (DRS=00)
osc_hi_1
osc_hi_1
Mid range (DRS=01)
1464 × f
2197 × f
2929 × f
732 × f
= 8 MHz, f
= 8 MHz, f
fll_ref
fll_ref
fll_ref
fll_ref
pll_ref
pll_ref
Preliminary
=
=
PLL
± 1.49
± 4.47
48.0
Min.
2.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
23.99
47.97
71.99
95.98
1060
1350
TBD
TBD
Typ.
600
120
600
50
—
—
—
—
—
—
1075(1/
± 2.98
± 5.97
0.15 +
f
Max.
TBD
TBD
pll_ref
100
4.0
—
—
—
—
—
—
—
—
—
—
1
Freescale Semiconductor, Inc.
)
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ms
µA
µA
ms
ps
ps
ps
ps
ps
ps
%
%
Notes
5,
10
10
11
7
7
8
9
9
6