PK60X256VMD100 Freescale Semiconductor, PK60X256VMD100 Datasheet - Page 22

• Manufacturer Part Number: PK60X256VMD100
• Description: IC ARM CORTEX MCU 256K 144-MAP
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of PK60X256VMD100

• Core Processor: ARM Cortex-M4
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, SDHC, SPI, UART/USART, USB, USB OTG
• Peripherals: DMA, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 100
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 33x16b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 144-LBGA
• Processor Series: Kinetis
• Core: ARM Cortex M4
• Data Ram Size: 64 KB
• Interface Type: UART, SPI, I2C, I2S, CAN
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 100
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

General
5.2.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CAN, CMT, IEEE 1588 timer, and I
22
FB_CLK
Symbol
Symbol
f
f
LPTMR
FLASH
FlexBus clock
Flash clock
LPTMR clock
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
Port rise and fall time (low drive strength)
Description
Description
• Slew disabled
• Slew enabled
• Slew disabled
• Slew enabled
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
• 1.71 ≤ V
• 2.7 ≤ V
Table 9. Device clock specifications (continued)
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Table 10. General switching specifications
DD
DD
DD
DD
DD
DD
DD
DD
≤ 3.6V
≤ 3.6V
≤ 3.6V
≤ 3.6V
≤ 2.7V
≤ 2.7V
≤ 2.7V
≤ 2.7V
2
C signals.
Preliminary
Min.
Min.
100
100
1.5
16
—
—
—
—
—
—
—
—
—
—
—
2
Max.
Max.
TBD
TBD
TBD
TBD
25
12
36
32
36
—
—
—
—
—
2
1
Freescale Semiconductor, Inc.
Bus clock
Bus clock
cycles
cycles
MHz
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Notes
1
2
2
2
3
4