AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 656

• Manufacturer Part Number: AT91SAM7SE256B-CUR
• Description: IC ARM7 MCU FLASH 256K 128-LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256B-CUR

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Processor Series: SAM7SE256
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 88
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: - 40 C to + 85 C
• Processor To Be Evaluated: AT91SAM7SE256B
• Supply Current (max): 60 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

43.2.7
43.2.7.1
43.2.7.2
43.2.7.3
43.2.7.4
656
SAM7SE512/256/32 Preliminary
Synchronous Serial Controller (SSC)
SSC: Periodic Transmission Limitations in Master Mode
SSC: Transmitter Limitations in Slave Mode
SSC: Transmitter Limitations in Slave Mode
SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer
If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not
sent.
None.
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when the starting edge (rising or falling) of synchro has a Start Delay equal to zero.
None.
If TK is programmed as an input and TF is programmed as an output and requested to be set to
low/high during data emission, the Frame Synchro signal is generated one bit clock period after
the data start and one data bit is lost. This problem does not exist when generating a periodic
synchro.
The data need to be delayed for one bit clock period with an external assembly. In the following
schematic, TD, TK and NRST are SAM7SE signals, TXD is the delayed data to connect to the
device.
When the SSC receiver is used with the following conditions:
• the internal clock divider is used (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6222F–ATARM–14-Jan-11