AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 221
![IC ARM7 MCU FLASH 256K 128-LQFP](/photos/39/70/397007/bga-144_sml.jpg)
AT91SAM7SE256B-CUR
Manufacturer Part Number
AT91SAM7SE256B-CUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-CUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 24-2. Parity Generation for 512/1024/2048/4096 8-bit Words1
6222F–ATARM–14-Jan-11
(page size -1 )th byte
(page size -2 )th byte
(page size -3 )th byte
Page size th byte
Page size = 512 Px = 2048
Page size = 1024 Px = 4096
Page size = 2048 Px = 8192
Page size = 4096 Px = 16384
4 th byte
2nd byte
3rd byte
1st byte
bit words. Of the 32 ECC bits, 26 bits are for line parity and 6 bits are for column parity. They are
generated according to the schemes shown in
To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows.
Bit7
Bit7
Bit7
Bit7
Bit7
Bit7
Bit7
Bit7
P1
Page size = 2
P2
for i =0 to n
begin
end
Bit6
Bit6
Bit6
Bit6
Bit6
Bit6
Bit6
Bit6
for (j = 0 to page_size_byte)
begin
P1'
if(j[i] ==1)
else
end
P[2
P[2
P4
i+3
i+3
Bit5
Bit5
Bit5
Bit5
Bit5
Bit5
Bit5
Bit5
P1
]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
]’=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
P2'
n
Bit4
Bit4
Bit4
Bit4
Bit4
Bit4
Bit4
Bit4
P1'
bit2(+)bit1(+)bit0(+)P[2
bit2(+)bit1(+)bit0(+)P[2
Bit3
Bit3
Bit3
Bit3
Bit3
Bit3
Bit3
Bit3
P1
P2
P1=bit7(+)bit5(+)bit3(+)bit1(+)P1
P2=bit7(+)bit6(+)bit3(+)bit2(+)P2
P4=bit7(+)bit6(+)bit5(+)bit4(+)P4
P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1'
P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2'
P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4'
Bit2
Bit2
Bit2
Bit2
Bit2
Bit2
Bit2
Bit2
SAM7SE512/256/32 Preliminary
P1'
P4'
Bit1
Bit1
Bit1
Bit1
Bit1
Bit1
Bit1
Bit1
P1
P2'
Figure 24-2
Bit0
Bit0
Bit0
Bit0
Bit0
Bit0
Bit0
Bit0
P1'
i+3
i+3
]
P8
P8'
P8
P8'
P8
P8'
P8
P8'
]'
and
P16'
P16'
P16
P16
Figure
P32
P32
P32
24-3.
PX
PX'
221
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