AT91SAM7SE256B-CUR Atmel, AT91SAM7SE256B-CUR Datasheet - Page 150
AT91SAM7SE256B-CUR
Manufacturer Part Number
AT91SAM7SE256B-CUR
Description
IC ARM7 MCU FLASH 256K 128-LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7SE256-AU.pdf
(673 pages)
Specifications of AT91SAM7SE256B-CUR
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
EBI/EMI, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
88
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Processor Series
SAM7SE256
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
SPI, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
88
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 85 C
Processor To Be Evaluated
AT91SAM7SE256B
Supply Current (max)
60 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 150 of 673
- Download datasheet (11Mb)
21.7.3
21.7.3.1
21.7.3.2
150
SAM7SE512/256/32 Preliminary
8-bit NAND Flash
Hardware Configuration
Software Configuration
(ANY PIO)
NANDOE
NANDWE
(ANY PIO)
D[0..7]
CLE
ALE
The following configuration must be respected:
• CLE, ALE, NANDOE and NANDWE signals are multiplexed with PIO lines and thus the
• Assign the EBI CS3 to the NAND Flash by setting the bit EBI_CS3A in the EBI Chip Select
• Reserve A21/A22 for ALE/CLE functions. Address and Command Latches are controlled
• Configure a PIO line as an input to manage the Ready/Busy signal.
• Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode according to NAND
dedicated PIOs must be programmed in peripheral mode in the PIO controller.
Assignment Register.
respectively by setting to 1 the address bit A21 and A22 during accesses.
Flash timings, the data bus width and the system bus frequency.
3V3
R1
R1
R2
R2
10K
10K
10K
10K
16
17
18
19
10
11
14
15
20
21
22
23
24
25
26
8
9
7
1
2
3
4
5
6
U1
U1
CLE
ALE
RE
WE
CE
R/B
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
TSOP48 PACKAGE
2 Gb
K9F2G08U0M
K9F2G08U0M
VCC
VCC
PRE
VSS
VSS
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
29
30
31
32
41
42
43
44
48
47
46
45
40
39
38
35
34
33
28
27
37
12
36
13
D0
D1
D2
D3
D4
D5
D6
D7
C1
C1
100NF
100NF
3V3
C2
C2
100NF
100NF
6222F–ATARM–14-Jan-11
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