ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 251
ATMEGA128A-ANR
Manufacturer Part Number
ATMEGA128A-ANR
Description
IC MCU AVR 128K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-ANR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Core
AVR8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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24.3
8151H–AVR–02/11
TAP – Test Access Port
The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins
constitute the Test Access Port –– TAP. These pins are:
Figure 24-1. Block Diagram
• TMS: Test mode select. This pin is used for navigating through the TAP-controller state
• TCK: Test clock. JTAG operation is synchronous to TCK.
• TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register.
• The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is
• When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the
• For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is
machine.
(Scan Chains).
not provided.
TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP
input signals are internally pulled high and the JTAG is enabled for Boundary-scan and
programming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG
TAP controller is not shifting data, and must therefore be connected to a pull-up resistor or
other hardware having pull-ups (for instance the TDI-input of the next device in the scan
chain). The device is shipped with this fuse programmed.
monitored by the debugger to be able to detect External Reset sources. The debugger can
also pull the RESET pin low to reset the whole system, assuming only open collectors on the
Reset line are used in the application.
TDI
TDO
TCK
TMS
CONTROLLER
M
U
X
TAP
DEVICE BOUNDARY
INSTRUCTION
BREAKPOINT
SCAN CHAIN
REGISTER
REGISTER
REGISTER
BYPASS
ID
ADDRESS
DECODER
JTAG PROGRAMMING
MEMORY
FLASH
AND CONTROL
BREAKPOINT
OCD STATUS
INTERFACE
UNIT
Address
Data
I/O PORT 0
I/O PORT n
INTERNAL
FLOW CONTROL
CHAIN
SCAN
UNIT
BOUNDARY SCAN CHAIN
PC
Instruction
JTAG / AVR CORE
COMMUNICATION
PERIPHERAL
INTERFACE
AVR CPU
DIGITAL
UNITS
ATmega128A
251
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