ATMEGA128A-ANR Atmel, ATMEGA128A-ANR Datasheet - Page 172
ATMEGA128A-ANR
Manufacturer Part Number
ATMEGA128A-ANR
Description
IC MCU AVR 128K FLASH 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA128A-ANR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Core
AVR8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Company
Part Number
Manufacturer
Quantity
Price
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8151H–AVR–02/11
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
below:
Table 19-2.
• Bit 2 – CPHA: Clock Phase
The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
ity is summarized below:
Table 19-3.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have
no effect on the slave. The relationship between SCK and the Oscillator Clock frequency f
shown in the following table:
Table 19-4.
SPI2X
CPOL
CPHA
0
0
0
0
1
0
1
0
1
CPOL functionality
CPHA functionality
Relationship Between SCK and the Oscillator Frequency
Figure 1
SPR1
0
0
1
1
0
and
Figure 2
Leading edge
Leading edge
Figure 1
Sample
Falling
Rising
Setup
for an example. The CPOL functionality is summarized
SPR0
and
0
1
0
1
0
Figure 2
SCK Frequency
f
f
f
f
f
for an example. The CPHA functional-
osc
osc
osc
osc
osc
/
/
/
/
/
4
128
2
16
64
ATmega128A
Trailing edge
Trailing edge
Sample
Falling
Rising
Setup
osc
172
is
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