ATMEGA128A-AN Atmel, ATMEGA128A-AN Datasheet - Page 305

• Manufacturer Part Number: ATMEGA128A-AN
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.8.2
8151H–AVR–02/11
Data Polling Flash
When reading data from the ATmega128A, data is clocked on the falling edge of SCK. See
ure 26-8
To program and verify the ATmega128A in the SPI Serial Programming mode, the following
sequence is recommended (See four byte instruction formats in
When a page is being programmed into the Flash, reading an address location within the page
being programmed will give the value $FF. At the time the device is ready for a new page, the
programmed value will read correctly. This is used to determine when the next page can be writ-
ten. Note that the entire page is written simultaneously and any address within the page can be
used for polling. Data polling of the Flash will not work for the value $FF, so when programming
1. Power-up sequence:
2. Wait for at least 20ms and enable SPI Serial Programming by sending the Program-
3. The SPI Serial Programming instructions will not work if the communication is out of
4. The Flash is programmed one page at a time. The page size is found in
5. The EEPROM array is programmed one byte at a time by supplying the address and
6. Any memory location can be verified by using the Read instruction which returns the
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
As an alternative to using the RESET signal, PEN can be held low during Power-on
Reset while SCK is set to “0”. In this case, only the PEN value at Power-on Reset is
important. If the programmer cannot guarantee that SCK is held low during power-up,
the PEN method cannot be used. The device must be powered down in order to com-
mence normal operation when using this method.
ming Enable serial instruction to pin MOSI.
synchronization. When in sync. the second byte ($53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
FOUR bytes of the instruction must be transmitted. If the $53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
page
address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is
applied for given address. The Program Memory Page is stored by loading the Write
Program Memory Page instruction with the 9MSB of the address. If polling is not used,
the user must wait at least t
Note: If other commands than polling (read) are applied before any write operation
(Flash, EEPROM, Lock bits, Fuses) is completed, may result in incorrect programming.
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling is not used, the user must
wait at least t
erased device, no $FFs in the data file(s) need to be programmed.
content at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
for timing details.
296. The memory page is loaded one byte at a time by supplying the 7 LSB of the
CC
power off.
WD_EEPROM
CC
before issuing the next byte. (See
and GND while RESET and SCK are set to “0”. In some sys-
WD_FLASH
before issuing the next page. (See
Table
Table
26-14). In a chip
ATmega128A
26-8):
Table 26-11 on
Table
26-14).
Fig-
305