ATMEGA128A-AN Atmel, ATMEGA128A-AN Datasheet - Page 268

• Manufacturer Part Number: ATMEGA128A-AN
• Description: IC MCU AVR 128K FLASH 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA128A-AN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8151H–AVR–02/11
Note:
If the ADC is not to be used during scan, the recommended input values from
be used. The user is recommended not to use the Differential Gain stages during scan. Switch-
Cap based gain stages require fast operation and accurate timing which is difficult to obtain
when used in a scan chain. Details concerning operations of the differential gain stage is there-
fore not provided.
The AVR ADC is based on the analog circuitry shown in
imation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is
usually to ensure that an applied analog voltage is measured within some limits. This can easily
be done without running a successive approximation algorithm: apply the lower limit on the digi-
tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit
on the digital DAC[9:0] lines, and verify the output from the comparator to be high.
The ADC need not be used for pure connectivity testing, since all analog inputs are shared with
a digital port pin as well.
When using the ADC, remember the following
As an example, consider the task of verifying a 1.5V ±5% input signal at ADC channel 3 when
the power supply is 5.0V and AREF is externally connected to V
The recommended values from
rithm in
column “Actions” describes what JTAG instruction to be used before filling the Boundary-scan
Register with the succeeding columns. The verification should be done on the data scanned out
when scanning in the data on the same row in the table.
Table 24-6.
Step
1
2
3
4
5
• The Port Pin for the ADC channel in use must be configured to be an input with pull-up
• In normal mode, a dummy conversion (consisting of 10 comparisons) is performed when
• The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal
disabled to avoid signal contention.
enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before
controlling/observing any ADC signal, or perform a dummy conversion before using the first
result.
low (Sample mode).
Incorrect setting of the switches in
part. There are several input choices to the S&H circuitry on the negative input of the output com-
parator in
reference source, or Ground.
Table
Actions
SAMPLE_P
RELOAD
EXTEST
Algorithm for Using the ADC
24-6. Only the DAC and Port Pin values of the Scan Chain are shown. The
The lower limit is:
The upper limit is:
Figure
ADCEN
1
1
1
1
1
24-13. Make sure only one path is selected from either one ADC pin, Bandgap
DAC
0x200
0x200
0x200
0x123
0x123
Table 24-5
1024 1.5V 0,95 5V
1024 1.5V 1.05 5V
Figure 24-13
MUXEN
0x08
0x08
0x08
0x08
0x08
⋅
⋅
are used unless other values are given in the algo-
⋅
⋅
HOLD
1
0
1
1
1
will make signal contention and may damage the
⁄
⁄
Figure 24-13
=
PRECH
1
1
1
1
0
=
291
323
CC
=
=
.
0x123
0x143
PA3.
Data
0
0
0
0
0
with a successive approx-
ATmega128A
PA3.
Control
0
0
0
0
0
Table 24-5
PA3.
Pullup_
Enable
0
0
0
0
0
should
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