ATMEGA165PV-8ANR Atmel, ATMEGA165PV-8ANR Datasheet - Page 62
![IC MCU AVR 16K 8MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA165PV-8ANR
Manufacturer Part Number
ATMEGA165PV-8ANR
Description
IC MCU AVR 16K 8MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165PV-8ANR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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12.2
12.2.1
8019K–AVR–11/10
Ports as General Digital I/O
Configuring the Pin
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 12-2. General Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
Description” on page
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
:
79, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
(1)
SLEEP
SYNCHRONIZER
D
L
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
Q
Q
D
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
PINxn
WRITE PINx REGISTER
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
RRx
Figure 12-2
ATmega165P
PUD
clk
WDx
RDx
RPx
1
0
I/O
shows a func-
WPx
WRx
“Register
I/O
,
62
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