ATMEGA165PV-8ANR Atmel, ATMEGA165PV-8ANR Datasheet - Page 268
![IC MCU AVR 16K 8MHZ 64TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA165PV-8ANR
Manufacturer Part Number
ATMEGA165PV-8ANR
Description
IC MCU AVR 16K 8MHZ 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA165PV-8ANR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8019K–AVR–11/10
Table 25-4.
Note:
Table 25-5.
Note:
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
Fuse High Byte
OCDEN
JTAGEN
SPIEN
WDTON
EESAVE
BOOTSZ1
BOOTSZ0
BOOTRST
Fuse Low Byte
CKDIV8
CKOUT
SUT1
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
(1)
1. The SPIEN Fuse is not accessible in serial programming mode.
2. The default value of BOOTSZ1..0 results in maximum Boot Size. See
3. See
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits
5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This
1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See
3. The CKOUT Fuse allow the system clock to be output on PORTE7. See
4. See
(3)
(4)
(4)
(3)
(5)
for details.
and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to
be running in all sleep modes. This may increase the power consumption.
to avoid static current at the TDO pin in the JTAG interface.
See
page 31
on page 33
Fuse High Byte
Fuse Low Byte
“WDTCR – Watchdog Timer Control Register” on page 50
Table 26-4 on page 302
“System Clock Prescaler” on page 33
for details.
Bit No
Bit No
7
6
5
4
3
2
1
0
7
6
5
4
1
for details.
3
2
0
Description
Enable OCD
Enable JTAG
Enable Serial Program and Data
Downloading
Watchdog Timer always on
EEPROM memory is preserved
through the Chip Erase
Select Boot Size (see
on page 262
Select Boot Size (see
on page 262
Select Reset Vector
Description
Divide clock by 8
Clock output
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
for details.
for details)
for details)
Table 24-6
Table 24-6
for details.
Default Value
0 (programmed)
1 (unprogrammed)
1 (unprogrammed)
0 (programmed)
0 (programmed)
0 (programmed)
1 (unprogrammed)
0 (programmed)
Default Value
1 (unprogrammed, OCD disabled)
0 (programmed, JTAG enabled)
0 (programmed, SPI prog.
enabled)
1 (unprogrammed)
1 (unprogrammed, EEPROM not
preserved)
0 (programmed)
0 (programmed)
1 (unprogrammed)
for details.
ATmega165P
Table 24-6 on page 262
“Clock Output Buffer”
(1)
(2)
(2)
(2)
(2)
(2)
(1)
(2)
Table 7-9 on
268
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