ATTINY5-MAH Atmel, ATTINY5-MAH Datasheet - Page 98

• Manufacturer Part Number: ATTINY5-MAH
• Description: IC MCU AVR 512B FLASH 8UDFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY5-MAH

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Peripherals: POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 512B (256 x 16)
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-UFDFN Exposed Pad
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

14.3.1
98
ATtiny4/5/9/10
Enabling
The TPI is accessed via three pins, as follows:
In addition, the V
device. See
Figure 14-2. Using an External Programmer for In-System Programming via TPI
NVM can be programmed at 5V, only. In some designs it may be necessary to protect compo-
nents that can not tolerate 5V with, for example, series resistors.
The following sequence enables the Tiny Programming Interface (see
Figure 14-3. Sequence for enabling the Tiny Programming Interface
RESET
TPICLK
TPIDATA
• Apply 5V between V
• Depending on the method of reset to be used:
• Wait t
• Keep the TPIDATA pin high for 16 TPICLK cycles
– Either: wait t
– Or: if the RSTDISBL configuration bit has been programmed, apply 12V to the
RESET:
TPICLK:
TPIDATA:
This will reset the device and enable the TPI physical layer. The RESET pin must
then be kept low for the entire programming session
RESET pin. The RESET pin must be kept at 12V for the entire programming session
RST
Figure
(see
CONN
TPI
CC
Table 16-4 on page
14-2.
and GND pins must be connected between the external programmer and the
TOUT
Tiny Programming Interface enable input
Tiny Programming Interface clock input
Tiny Programming Interface data input/output
t
CC
RST
(see
and GND
Table 16-4 on page
APPLICATION
120)
+5V
120) and then set the RESET pin low.
16 x TPICLK CYCLES
TPIDATA/PB0
GND
TPICLK/PB1
ATtiny4/5/9/10
PB3/RESET
Figure 14-3
PB2
V
CC
for guidance):
8127D–AVR–02/10