ATTINY5-MAH Atmel, ATTINY5-MAH Datasheet - Page 104
![IC MCU AVR 512B FLASH 8UDFN](/photos/12/32/123206/8-udfn-8ma4_sml.jpg)
ATTINY5-MAH
Manufacturer Part Number
ATTINY5-MAH
Description
IC MCU AVR 512B FLASH 8UDFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY5-MAH
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Peripherals
POR, PWM, WDT
Number Of I /o
4
Program Memory Size
512B (256 x 16)
Program Memory Type
FLASH
Ram Size
32 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-UFDFN Exposed Pad
Core
AVR8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
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14.5.2
14.5.3
14.5.4
14.5.5
104
ATtiny4/5/9/10
SST - Serial STore to data space using indirect addressing
SSTPR - Serial STore to Pointer Register
SIN - Serial IN from i/o space using direct addressing
SOUT - Serial OUT to i/o space using direct addressing
The SST instruction uses indirect addressing to store into data space the byte that is shifted into
the physical layer shift register. The data space location is pointed by the Pointer Register (PR),
where the address must have been stored before the operation. The Pointer Register can be
either left unchanged by the operation, or it can be post-incremented, as shown in
Table 14-3.
The SSTPR instruction stores the data byte that is shifted into the physical layer shift register to
the Pointer Register (PR). The address bit of the instruction specifies which byte of the Pointer
Register is accessed, as shown in
Table 14-4.
The SIN instruction loads data byte from the I/O space to the shift register of the physical layer
for serial read-out. The instuction uses direct addressing, the address consisting of the 6
address bits of the instruction, as shown in
Table 14-5.
The SOUT instruction stores the data byte that is shifted into the physical layer shift register to
the I/O space. The instruction uses direct addressing, the address consisting of the 6 address
bits of the instruction, as shown in
Table 14-6.
Operation
DS[PR]
DS[PR]
Operation
PR[a]
Operation
data
Operation
I/O[a]
←
←
←
←
←
I/O[a]
data
data
data
data
The Serial Store to Data Space (SLD) Instruction
The Serial Store to Pointer Register (SSTPR) Instruction
The Serial IN from i/o space (SIN) Instruction
The Serial OUT to i/o space (SOUT) Instruction
Opcode
0110 0000
0110 0100
Opcode
0110 100a
Opcode
0aa1 aaaa
Opcode
1aa1 aaaa
Table
Table
14-6.
14-4.
Table
Remarks
PR
PR
Remarks
Bit ‘a’ addresses Pointer Register byte
Remarks
Bits marked ‘a’ form the direct, 6-bit addres
Remarks
Bits marked ‘a’ form the direct, 6-bit addres
14-5.
←
←
PR
PR + 1
Register
Unchanged
Post increment
8127D–AVR–02/10
Table
14-3.
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