ATTINY5-MAH Atmel, ATTINY5-MAH Datasheet - Page 70

• Manufacturer Part Number: ATTINY5-MAH
• Description: IC MCU AVR 512B FLASH 8UDFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY5-MAH

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Peripherals: POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 512B (256 x 16)
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-UFDFN Exposed Pad
• Core: AVR8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

11.9
70
Timer/Counter Timing Diagrams
ATtiny4/5/9/10
Using the ICR0 Register for defining TOP works well when using fixed TOP values. By using
ICR0, the OCR0A Register is free to be used for generating a PWM output on OC0A. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCR0A as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-
forms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and
an inverted PWM output can be generated by setting the COM0x1:0 to three (See
page
port pin is set as output (DDR_OC0x). The PWM waveform is generated by setting (or clearing)
the OC0x Register at the compare match between OCR0x and TCNT0 when the counter incre-
ments, and clearing (or setting) the OC0x Register at compare match between OCR0x and
TCNT0 when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCR0x Register is updated with the OCR0x buffer value (only for
modes utilizing double buffering).
ting of OCF0x.
Figure 11-12. Timer/Counter Timing Diagram, Setting of OCF0x, no Prescaling
OCRnx
TCNTn
OCFnx
(clk
clk
clk
I/O
I/O
Tn
75). The actual OC0x value will only be visible on the port pin if the data direction for the
/1)
OCRnx - 1
f
OCnxPFCPWM
Figure 11-12 on page 70
OCRnx
OCRnx Value
=
---------------------------- -
2 N TOP
⋅
f
clk_I/O
⋅
shows a timing diagram for the set-
OCRnx + 1
T0
) is therefore shown as a
OCRnx + 2
Table 11-4 on
8127D–AVR–02/10