NUC120LD2BN Nuvoton Technology Corporation of America, NUC120LD2BN Datasheet - Page 259
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NUC120LD2BN
Manufacturer Part Number
NUC120LD2BN
Description
IC MCU 32BIT 64KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC120LD2BN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
31
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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5.6
5.6.1
I
exchange between devices. The I
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up 1.0
Mbps.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a
byte-by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is
sampled during the high period of SCL; therefore, the SDA line may be changed only during the
low period of SCL and must be held stable during the high period of SCL. A transition on the SDA
line while SCL is high is interpreted as a command (START or STOP). Please refer to the Figure
5-17 for more detail I
The device’s on-chip I
specification. The I
in I2CON should be set to '1'. The I
Pull up resistor is needed for I
used as I
2
C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
I
2
C Serial Interface Controller (Master/Slave) (I
Overview
2
C port, user must set the pins function to I
NuMicro™ NUC100 Series Technical Reference Manual
2
C port handles byte transfers autonomously. To enable this port, the bit ENS1
2
C BUS Timing.
2
C logic provides the serial interface that meets the I
2
C operation as these are open drain pins. When the I/O pins are
Figure 5-17 I
2
2
C H/W interfaces to the I
C standard is a true multi-master bus including collision
- 259 -
2
C Bus Timing
2
C in advance.
Publication Release Date: Oct 22, 2010
2
C)
2
C bus via two pins: SDA and SCL.
2
C bus standard mode
Revision V1.06
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